AD9287BCPZRL-100 AD [Analog Devices], AD9287BCPZRL-100 Datasheet - Page 6

• Manufacturer Part Number: AD9287BCPZRL-100
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: AD [Analog Devices]

AD9287
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
Can be adjusted via the SPI interface.
t
SAMPLE
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data to Data Skew
(t
Wake-Up Time (Standby)
Wake-Up Time (Power Down)
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
DATA-MAX
/16 is based on the number of bits multiplied by 2; delays are based on half duty cycles.
2
− t
1
F
R
) (20% to 80%)
DATA-MIN
) (20% to 80%)
A
)
)
PD
DATA
2
FRAME
)
)
EL
3
EH
)
)
3
FCO
)
CPD
)
)
3
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
Min
100
2.0
2.0
(t
(t
SAMPLE
SAMPLE
Rev. 0 | Page 6 of 52
/16) − 300
/16) − 300
Typ
5
5
2.7
300
300
2.7
t
(t
(t
(t
±50
600
375
10
500
<1
2
FCO
SAMPLE
SAMPLE
SAMPLE
AD9287-100
+
/16)
/16)
/16)
Max
10
3.5
3.5
(t
(t
±150
SAMPLE
SAMPLE
/16) + 300
/16) + 300
Unit
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
ps
ps rms
CLK cycles
MSPS
MSPS
CLK cycles