AD9287BCPZRL-100 AD [Analog Devices], AD9287BCPZRL-100 Datasheet - Page 5

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AD9287BCPZRL-100

Manufacturer Part Number
AD9287BCPZRL-100
Description
Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
Manufacturer
AD [Analog Devices]
Datasheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (PDWN, SCLK/DTP)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO/ODM)
LOGIC OUTPUT (SDIO/ODM)
DIGITAL OUTPUTS (D+, D−), (ANSI-644)
DIGITAL OUTPUTS (D+, D−),
1
2
See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
This is specified for LVDS and LVPECL only.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
(Low Power, Reduced Signal Option)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
1
OH
OL
= 50 μA)
= 50 μA)
OS
OS
2
)
)
OD
OD
)
)
1
1
Rev. 0 | Page 5 of 52
Temp
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Min
250
1.2
1.2
1.2
0
1.79
247
1.125
150
1.10
CMOS/LVDS/LVPECL
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
LVDS
LVDS
AD9287-100
Offset binary
Offset binary
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
Unit
mV p-p
V
pF
V
V
pF
V
V
pF
V
V
pF
V
V
mV
V
mV
V
AD9287

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