AD9287BCPZRL-100 AD [Analog Devices], AD9287BCPZRL-100 Datasheet - Page 23

• Manufacturer Part Number: AD9287BCPZRL-100
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: AD [Analog Devices]

Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
Figure 51. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
–500
–200
500
100
200
100
–100ps
–150ps
50
50
0
0
0
0
–1.0ns
–1.0ns
Greater than 24 Inches on Standard FR-4
EYE: ALL BITS
EYE: ALL BITS
–100ps
than 24 Inches on Standard FR-4
–0.5ns
–0.5ns
–50ps
–0ps
–0ps
0ns
0ns
50ps
ULS: 10000/15600
0.5ns
ULS: 9600/15600
0.5ns
100ps
1.0ns
1.0ns
100ps
150ps
Rev. 0 | Page 23 of 52
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
If it is desired to change the output data format to twos
complement, see the Memory Map section.
Table 8. Digital Output Coding
Code
255
128
127
0
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 8 bits
times the sample clock rate, with a maximum of 800 Mbps
(8 bits × 100 MSPS = 800 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up for encode rates
lower than 10 MSPS via the SPI. This allows encode rates as low
as 5 MSPS. See the Memory Map section to enable this feature.
Figure 52. Data Eye for LVDS Outputs in ANSI Mode with 100 Ω Termination
on and Trace Lengths Greater than 24 Inches on Standard FR-4
–200
–400
(VIN+) − (VIN−), Input
Span = 2 V p-p (V)
+1.00
0.00
−0.007813
−1.00
400
200
100
–150ps
50
0
0
–1.0ns
EYE: ALL BITS
–100ps
–0.5ns
–50ps
–0ps
0ns
Digital Output Offset Binary
(D11 ... D0)
1111 1111
1000 0000
0111 1111
0000 0000
50ps
0.5ns
ULS: 9599/15599
100ps
1.0ns
AD9287
150ps