AD9287BCPZRL-100 AD [Analog Devices], AD9287BCPZRL-100 Datasheet - Page 20

• Manufacturer Part Number: AD9287BCPZRL-100
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: AD [Analog Devices]

AD9287
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9287 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 42 shows one preferred method for clocking the AD9287.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9287 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9287 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 43. The AD9510/AD9511/AD9512/AD9513/AD9514/
AD9515 family of clock drivers offers excellent jitter performance.
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
50Ω
50Ω
1
1
50Ω RESISTORS ARE OPTIONAL.
50Ω RESISTORS ARE OPTIONAL.
1
1
Figure 42. Transformer Coupled Differential Clock
50Ω
0.1µF
Figure 43. Differential PECL Sample Clock
Figure 44. Differential LVDS Sample Clock
0.1µF
0.1µF
50Ω
0.1µF
0.1µF
50Ω
100Ω
1
1
ADT1–1WT, 1:1Z
MIN-CIRCUITS
CLK
CLK
CLK
CLK
PECL DRIVER
LVDS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
XFMR
0.1µF
240Ω
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9287
CLK+
CLK–
AD9287
AD9287
ADC
ADC
ADC
Rev. 0 | Page 20 of 52
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 45). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
CLOCK
CLOCK
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9287 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9287. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 10 clock cycles
to allow the DLL to acquire and lock to the new rate.
INPUT
INPUT
1
50Ω RESISTORS ARE OPTIONAL.
1
50Ω RESISTORS ARE OPTIONAL.
50Ω
50Ω
Figure 45. Single-Ended 1.8 V CMOS Sample Clock
Figure 46. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
0.1µF
1
1
0.1µF
0.1µF
CLK
CLK
CLK
CLK
CMOS DRIVER
CMOS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9287
AD9287
ADC
ADC