PCA9505 NXP [NXP Semiconductors], PCA9505 Datasheet
PCA9505
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PCA9505 Summary of contents
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... LEDs. Any of the 40 I/O ports can be configured as an input or output. Output ports are totem-pole and their logic state changes at the Acknowledge (bank change). The PCA9505 is identical to the PCA9506 except that it includes 100 k internal pull-up resistors on all the I/Os. The PCA9506 does not include the internal pull-ups on the I/Os to reduce power consumption when used as outputs or when the input is driven by a push-pull driver ...
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... C to +85 C operation I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA I Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages 3. Applications I Servers I RAID systems I ...
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... NXP Semiconductors 5. Block diagram SCL SDA RESET Fig 1. Block diagram of PCA9505/06 PCA9505_9506_3 Product data sheet PCA9505/PCA9506 LOW PASS INPUT FILTERS POWER-ON RESET All I/Os are set to inputs at power-up and RESET. Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT ...
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... Mx[y] INTERRUPT input port MANAGEMENT register polarity inversion register PCA9505 only IOx_y ESD protection diode V SS INT input port register data (Ix[y]) polarity register data (Px[y]) 002aab493 © NXP B.V. 2007. All rights reserved ...
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... PCA9505DGG PCA9506DGG 15 IO1_2 IO1_3 16 IO1_4 IO1_5 IO1_6 20 IO1_7 21 22 IO2_0 IO2_1 24 IO2_2 25 26 IO2_3 Rev. 03 — 6 June 2007 PCA9505/06 56 RESET 55 INT 54 IO4_7 53 IO4_6 52 IO4_5 IO4_4 49 IO4_3 48 IO4_2 47 IO4_1 IO4_0 44 IO3_7 43 IO3_6 42 IO3_5 ...
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... Rev. 03 — 6 June 2007 PCA9505/06 2 C-bus I/O port with RESET, OE and INT 42 IO4_3 41 IO4_2 40 IO4_1 IO4_0 37 IO3_7 36 IO3_6 35 IO3_5 ...
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... The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.2 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9505/06, which will be stored in the Command register. Fig 6. Command register PCA9505_9506_3 Product data sheet Pin description … ...
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... At power-up, this register defaults to 0x80, with the AI bit set to logic 1, and the lowest 7 bits set to logic 0. During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since these are read-only registers ...
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... Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT Access Description read only Input Port register bank 0 read only Input Port register bank 1 read only Input Port register bank 2 read only Input Port register bank 3 ...
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... Symbol Access I0[7:0] R I1[7:0] R I2[7:0] R I3[7:0] R I4[7:0] R Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT Access Description read/write Mask Interrupt register bank 0 read/write Mask Interrupt register bank 1 read/write Mask Interrupt register bank 2 read/write Mask Interrupt register bank 3 read/write Mask Interrupt register bank 4 ...
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... P2[7:0] R/W 0000 0000* P3[7:0] R/W 0000 0000* P4[7:0] R/W 0000 0000* Rev. 03 — 6 June 2007 PCA9505/06 2 C-bus I/O port with RESET, OE and INT Description Output Port register bank 0 Output Port register bank 1 Output Port register bank 2 Output Port register bank 3 Output Port register bank 4 Description Polarity Inversion register bank 0 ...
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... R/W 1111 1111* M2[7:0] R/W 1111 1111* M3[7:0] R/W 1111 1111* M4[7:0] R/W 1111 1111 internal Power-On Reset (POR) holds the PCA9505/06 DD has reached V DD POR 2 must be lowered below 0 reset the device C-bus state machine will be held in their default states until Rev. 03 — 6 June 2007 PCA9505/06 ...
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... The robust state machine does not respond until it sees a valid START condition and the 50 ns noise filter will filter out any insertion glitches. The PCA9505/06 will not cause corruption of active data on the bus, nor will the device be damaged or cause damage to devices already on the bus when similar featured devices are being used ...
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... C-bus Figure SDA SCL data line stable; data valid Figure 8). S START condition Figure 9). Rev. 03 — 6 June 2007 PCA9505/06 2 C-bus I/O port with RESET, OE and INT 7). change of data allowed mba607 P STOP condition © NXP B.V. 2007. All rights reserved. SDA SCL mba608 ...
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... In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Fig 10. Acknowledgement on the I 8.4 Bus transactions Data is transmitted to the PCA9505/06 registers using Write Byte transfers (see Figure 11, Read and Receive Byte transfers (see PCA9505_9506_3 ...
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SDA output bank START condition register bank 0 R selected acknowledge from slave acknowledge ...
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SDA START condition R acknowledge from slave The programming becomes effective at the acknowledge. Less ...
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... IO0_2 INT IO0_3 OE IO0_4 IO0_5 IO1_0 IO3_7 A2 IO4_0 A1 A0 IO4_7 V SS ALPHA NUMERIC KEYPAD Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT 5 V SUB-SYSTEM 1 (e.g., temp sensor) INT SUB-SYSTEM 2 (e.g., counter) RESET A ENABLE B SUB-SYSTEM 3 (e.g., alarm system) ALARM 24 LED MATRIX ...
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... SCL load kHz; SCL I/O = inputs PCA9505 only [1] no load Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT Min Max 0 0.5 5 0.5 5 0.5 5 ...
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... PCA9506 only PCA9505 only Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT Min Typ 0 4.5 V ...
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... A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V bridge the undefined region SCL’s falling edge. PCA9505_9506_3 Product data sheet 40-bit I Conditions Standard mode [1] [2] [4][5] [4][5] [7] output output Rev. 03 — 6 June 2007 PCA9505/06 2 C-bus I/O port with RESET, OE and INT 2 Fast mode C-bus Min Max Min 0 100 0 4 ...
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... MSB (A6) (A7 LOW HIGH 1 /f SCL SU;DAT HD;DAT and Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT t t HD;STA SU;STA SU;STO Sr STOP bit 0 acknowledge condition (R/W) (A) ( VD;DAT VD;ACK SU ...
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... PULSE GENERATOR R = load resistance load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance Z T generators. Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT ACK or read cycle t rst w(rst) t rst ...
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... PCA9505_9506_3 Product data sheet 2.5 scale (1) ( 0.28 0.2 0.2 14.1 6.2 0.5 0.17 0.1 0.1 13.9 6.0 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT detail 8.3 0.8 0.50 1 0.25 0.08 7.9 0.4 ...
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... (1) ( 8.1 4.45 8.1 4.45 0.5 6.5 7.9 4.15 7.9 4.15 REFERENCES JEDEC JEITA MO-220 - - - Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT detail 2 scale 0.5 6.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN ...
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... Package placement • Inspection and repair • Lead-free soldering versus PbSn soldering 16.3 Wave soldering Key characteristics in wave soldering are: PCA9505_9506_3 Product data sheet 2 40-bit I C-bus I/O port with RESET, OE and INT Rev. 03 — 6 June 2007 PCA9505/06 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 22. Rev. 03 — 6 June 2007 PCA9505/06 2 C-bus I/O port with RESET, OE and INT Figure 22) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... Inter IC bus Light Emitting Diode Machine Model Programmable Logic Controller Power-On Reset Pulse Width Modulation Redundant Array of Independent Disks Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved. ...
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... IO4_7”: added pull-up resistor for PCA9505 characteristics”, sub-section “Supply”: : added separate specifications for PCA9505 DD , standby current” to “I stb , LOW-level standby current” (applies to PCA9505 only) stbL characteristics”, sub-section “I/Os”: : added separate specifications for PCA9505 LIL Product data sheet Product data sheet Rev. 03 — ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 6 June 2007 PCA9505/06 2 C-bus I/O port with RESET, OE and INT © NXP B.V. 2007. All rights reserved ...
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... For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contact information . . . . . . . . . . . . . . . . . . . . 30 Contents Document identifier: PCA9505_9506_3 All rights reserved. Date of release: 6 June 2007 ...