PCA9505 NXP [NXP Semiconductors], PCA9505 Datasheet - Page 22

• Manufacturer Part Number: PCA9505
• Description: 40-bit I2C-bus I/O port with RESET, OE and INT
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
[5]
[6]
[7]
PCA9505_9506_3
Product data sheet
Fig 16. Definition of timing on the I
Fig 17. I
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
b
SDA
SCL
= total capacitance of one bus line in pF.
Rise and fall times refer to V
2
C-bus timing diagram
P
t
BUF
protocol
SDA
f
SCL
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
S
t
SU;STA
t
t
HD;STA
BUF
condition
t
LOW
START
(S)
t
HD;STA
IL
f
.
and V
2
C-bus
t
t
t
LOW
r
HD;DAT
t
r
IH
.
MSB
bit 7
(A7)
t
HIGH
Rev. 03 — 6 June 2007
t
t
HIGH
SU;DAT
t
f
1
/f
bit 6
(A6)
SCL
t
f
t
HD;DAT
t
SU;DAT
40-bit I
(R/W)
bit 0
t
VD;DAT
2
acknowledge
C-bus I/O port with RESET, OE and INT
Sr
(A)
t
SU;STA
t
HD;STA
t
VD;ACK
condition
STOP
(P)
PCA9505/06
t
SU;STO
002aab175
t
SP
t
SU;STO
© NXP B.V. 2007. All rights reserved.
002aaa986
f
is specified at
P
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