DAC1005D650HW/C1 NXP [NXP Semiconductors], DAC1005D650HW/C1 Datasheet - Page 11

• Manufacturer Part Number: DAC1005D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 5.
V
T
unless otherwise specified.
DAC1005D650_1
Product data sheet
Symbol
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
I
V
N
Input timing (see
f
t
t
t
Output timing
f
t
NCO frequency range; f
f
f
Low-power NCO frequency range; f
f
f
Dynamic performance; PLL on
SFDR
O(aux)
data
w(CLK)
h(i)
su(i)
s
s
NCO
step
NCO
step
amb
DDA(1V8)
O(aux)
DAC(aux)mono
= 40 C to +85 C; typical values measured at T
= V
Characteristics
DDD(1V8)
Parameter
auxiliary output current differential outputs
auxiliary output voltage compliance range
auxiliary DAC
monotonicity
data rate
CLK pulse width
input hold time
input set-up time
sampling frequency
settling time
NCO frequency
step frequency
NCO frequency
step frequency
spurious-free dynamic
range
Figure
= 1.8 V; V
s
10)
= 640 Msps
…continued
DDA(3V3)
DAC
= V
Conditions
guaranteed
Dual-port mode input
to 0.5 LSB
register value = 00000000h
register value = FFFFFFFFh
register value = 00000000h
register value = F8000000h
f
B = f
f
B = f
f
B = f
data
data
data
= 640 MHz
f
f
f
f
o
o
o
o
DD(IO)(3V3)
= 35 MHz at 0 dBFS
= 4 MHz at 0 dBFS
= 19 MHz at 0 dBFS
= 70 MHz at 0 dBFS
= 80 MHz; f
= 80 MHz; f
= 160 MHz; f
data
data
data
/ 2
/ 2
/ 2
Rev. 01 — 28 July 2009
= 3.3 V; AGND, DGND and GNDIO shorted together;
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
amb
s
s
s
= 320 Msps;
= 640 Msps;
= 25 C; R
= 640 Msps;
L
= 50 ; I
Test
I
C
D
C
C
C
C
C
D
D
D
D
D
D
D
C
I
I
C
[1]
O(fs)
= 20 mA; maximum sample rate; PLL on;
Min
-
0
-
-
1.5
1.1
1.1
-
-
-
-
-
-
-
-
-
-
-
-
DAC1005D650
Typ
2.2
-
10
-
-
-
-
-
20
0
640
0.149 -
0
620
20
82
76
75
82
Max
-
2
-
160
T
-
-
650
-
-
-
-
-
-
-
-
-
-
data
© NXP B.V. 2009. All rights reserved.
1.5 ns
Unit
mA
V
bit
MHz
ns
ns
Msps
ns
MHz
MHz
Hz
MHz
MHz
MHz
dBc
dBc
dBc
dBc
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