DAC1005D650HW/C1 NXP [NXP Semiconductors], DAC1005D650HW/C1 Datasheet - Page 13

• Manufacturer Part Number: DAC1005D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
10. Application information
DAC1005D650_1
Product data sheet
10.2.1 Protocol description
10.1 General description
10.2 Serial interface (SPI)
The DAC1005D650 is a dual 10-bit DAC operating at up to 650 Msps. Each DAC consists
of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary
weighted sub-DAC.
With an input data rate of up to 160 MHz, and a maximum output sampling rate of
650 Msps, the DAC1005D650 allows more flexibility for wide bandwidth and multi-carrier
systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1005D650
simplifies the frequency selection of the system. This is also possible because of the 2 ,
4 and 8 interpolation filters that remove undesired images.
Two modes are available for the digital input. In the Dual-port mode, each DAC uses its
own data input line. In Interleaved mode, both DACs use the same data input line.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current (I
reference is available for the reference current which is externally adjustable using pin
VIRES.
There are embedded features which provide analog offset correction (internal auxiliary
DACs), digital offset control and gain adjustment. All the functions can be set using a SPI.
The DAC1005D650 operates at both 3.3 V and 1.8 V using separate digital and analog
power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant.
The DAC1005D650 serial interface is a synchronous serial communication port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that define the operating modes of the chip in both write and read modes.
This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire
type (SDIO and SDO as unidirectional pin, input and output port respectively). In both
configurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select
bar.
Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW
assertion to drive the chip with between 2 to 5 bytes, depending on the content of the
instruction byte (see
Table
Rev. 01 — 28 July 2009
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
7).
DAC1005D650
O(fs)
) up to 20 mA. An internal
© NXP B.V. 2009. All rights reserved.
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