DAC1005D650HW/C1 NXP [NXP Semiconductors], DAC1005D650HW/C1 Datasheet - Page 19

• Manufacturer Part Number: DAC1005D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1005D650_1
Product data sheet
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Default settings are shown highlighted.
Table 20.
Table 21.
Bit
7 to 0 FREQ_NCO[23:16]
Bit
7 to 0 FREQ_NCO[31:24]
Bit
7 to 0 PH_NCO[7:0]
Bit
7 to 0 PH_NCO[15:8]
Bit
7
6
5 to 3 DAC_A_OFFSET[2:0]
Bit
7 to 6 DAC_A_GAIN_COARSE[1:0] R/W
5 to 0 DAC_A_GAIN_FINE[5:0]
Bit
7 to 6 DAC_A_GAIN_COARSE[3:2] R/W
5 to 0 DAC_A_OFFSET[8:3]
Symbol
Symbol
Symbol
Symbol
Symbol
DAC_A_PD
DAC_A_SLEEP
Symbol
Symbol
FREQNCO_UISB register (address 05h) bit description
FREQNCO_MSB register (address 06h) bit description
PHINCO_LSB register (address 07h) bit description
PHINCO_MSB register (address 08h) bit description
DAC_A_Cfg_1 register (address 09h) bit description
DAC_A_Cfg_2 register (address 0Ah) bit description
DAC_A_Cfg_3 register (address 0Bh) bit description
Rev. 01 — 28 July 2009
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
R/W
R/W
Access Value Description
R/W
Access Value
R/W
-
-
-
-
0
1
0
1
-
-
-
most significant 8 bits for the NCO phase setting
-
-
upper intermediate 8 bits for the NCO
frequency setting
most significant 8 bits for the NCO frequency
setting
lower 8 bits for the NCO phase setting
DAC A power
DAC A Sleep mode
lower 3 bits for the DAC A offset
on
off
disabled
enabled
least significant 2 bits for the DAC A gain
setting for coarse adjustment
the 6 bits for the DAC A fine adjustment
gain setting
Description
most significant 2 bits for the DAC A gain
setting for coarse adjustment
most significant 6 bits for the DAC A
offset
DAC1005D650
© NXP B.V. 2009. All rights reserved.
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