DSP56800ERM FREESCALE [Freescale Semiconductor, Inc], DSP56800ERM Datasheet - Page 91

• Manufacturer Part Number: DSP56800ERM
• Description: 16-bit Digital Signal Controllers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Part 9 Joint Test Action Group (JTAG)
9.1 56F8013 Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific
BSDL information.
The TRST pin is not available in this package. The pin is tied to V
The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high
for five rising edges of TCK, as described in the 56F8000 Peripheral User Manual.
Part 10 Specifications
10.1 General Characteristics
The 56F8013 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The
term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels, combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to
105ºC ambient temperature over the following supply ranges:
V
Freescale Semiconductor
Preliminary
SS
= V
SS
A = 0V, V
DD
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
= V
DDA
Table 10-1
application
= 3.0–3.6V, CL < 50pF, f
56F8013 Technical Data, Rev. 2
are stress ratings only, and functional operation at the maximum
of
CAUTION
any
voltages
OP
= 32MHz
DD
higher
in the package.
than
56F8013 Information
10% during
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