ADSP-BF523C AD [Analog Devices], ADSP-BF523C Datasheet
ADSP-BF523C
Related parts for ADSP-BF523C
ADSP-BF523C Summary of contents
Page 1
... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Selectable ADC High Pass Filter TWI or SPI Interface Programmable Audio Data Interface Modes ...
Page 2
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C TABLE OF CONTENTS General Description ................................................. 3 CODEC Description ................................................. 3 CODEC Pin Descriptions ........................................ 15 CODEC Operation ................................................. 16 CODEC Resetting ............................................... 16 Clocking ........................................................... 16 Digital Audio Interfaces ....................................... 17 Master and Slave Mode Operation .......................... 21 Audio Data Sampling Rates ................................... 21 Software Control Interface .................................... 24 SPI Mode ....................................................... 24 TWI Mode ..................................................... 25 Power Down Modes ............................................ 25 Register Map ........................................................ 27 Specifications ........................................................ 31 Operating Conditions .......................................... 31 Power Consumption ...
Page 3
... Line level outputs are pro- vided along with anti-thump mute and power-up/power-down circuitry. The device is controlled by the ADSP-BF523C/ADSP- BF525C/ADSP-BF527C 2-wire (TWI) or 3-wire serial periph- eral interface (SPI). The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities ...
Page 4
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C The device is controlled by a TWI or SPI serial interface which provides access to all features including volume controls, mutes and extensive power management facilities. AVDD VMID AGND MICBIAS VOLUME MUTE RLINEIN MUTE MIC MICIN BOOST MUTE LLINEIN VOLUME MUTE OSCPD CLKIN OSC ...
Page 5
... Line Inputs The CODEC provides left and right channel line inputs (RLINEIN and LLINEIN). The inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external high-fidelity or audio equipment. ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Rev. PrC | Page June 2008 ...
Page 6
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C 1 F 5.6 K 5.6 K 220 5.6 K 5.6 K 220 pF 680 + R MIC 47 K AUDIO SERIAL DATA I/F 3 3-WIRE INTERFACE 2-WIRE INTERFACE 3-WIRE OR 2-WIRE MPU INTERFACE + LLINEIN + RLINEIN CODEC MICBIAS MICIN DACLRC DACDAT ADCDAT ADCLRC CODEC_BCLK CMODE CSB CSDA CSCL XTI/CODEC_MCLK XTO Figure 2. External Components Diagram Rev ...
Page 7
... LINMUTE/RINMUTE only mute the input to the ADC, which allows the line input signal to pass to the line output in bypass mode. ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Using software control, the gain between the line inputs and the ADC is logarithmically adjustable from + –34 1.5 dB steps. The ADC full scale input is 1.0 V(rms) at AVDD = 3 ...
Page 8
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Table 1. Line Input Software Control Register Address Bit Label Default Description 000 0000 4:0 LINVOL[4:0] 10111 Left Line LINMUTE 1 8 LRINBOTH 0 000 0001 4:0 RINVOL[4:0] 10111 Right Line RINMUTE 1 8 RLINBOTH 0 inputs. These allow a matched interface to the multi-bit over- sampling ADC and prevent high frequencies from aliasing into the audio band to degrade performance ...
Page 9
... The MICBIAS output is not active in standby mode. + VMID - AGND Figure 7. MICBIAS Internal Circuit ADSP-BF523C/ADSP-BF525C/ADSP-BF527C ADC The CODEC uses a multi-bit oversampled sigma-delta ADC. A single channel of the ADC is illustrated in the of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. ...
Page 10
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Digital Filter Characteristics on Page 39. The filter types are automatically configured depending on the sample rate chosen. See USB Mode Sample Rates on Page 23 When the high-pass filter is enabled the dc offset is continu- ously calculated and subtracted from the input signal. By setting HPOR, the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal ...
Page 11
... The CODEC has a stereo headphone output available on LHPOUT and RHPOUT. The output is designed for driving 16 Ω Ω headphones with maximum efficiency and low power consumption. The headphone output includes a high quality volume level adjustment and mute function. ADSP-BF523C/ADSP-BF525C/ADSP-BF527C The internal circuit is shown in FROM DAC VIA LINEOUT Table 6 ...
Page 12
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Software control is shown in Table 7. Table 7. Headphone Output Software Control Register Bit Label Default Description Address 000 0010 6:0 LHPVOL[6:0] 1111001 Left Channel Headphone Output Volume Control ( (1111111 steps down to –73 dB(0110000 ) 0000000 to 0101111 = MUTE 7 LZCEN 0 Left Channel Zero-Cross Detect Enable ...
Page 13
... Table 8. Bypass Mode Software Control Register Bit Label Default Description Address 000 0100 3 BYPASS 1 Bypass Switch (analog Enable Bypass 0 = Disable Bypass ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Figure 16. SIDETONE (OFF) BYPASS (ON) FROM LINE INPUTS DACSEL (OFF) FROM - DAC VMID + Figure 16. Signal Routing in Bypass Mode Rev ...
Page 14
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Sidetone Mode The sidetone mode routs the microphone input to the line and headphone outputs as shown in Figure 10 K MICIN VMID The sidetone mode allows the microphone input to be attenu- ated to the outputs for telephone and headset applications. The sidetone mode and attenuation are selected under software ...
Page 15
... Preliminary Technical Data CODEC PIN DESCRIPTIONS The ADSP-BF523C/ADSP-BF525C/ADSP-BF527C product adds CODEC signals to those listed in Table 1 of the standard product datasheet ADSP-BF522/523/524/525/526/527 revision PrD. Table 10. CODEC Pin Descriptions Pin Name Type Function CODEC CODEC_CLKOUT O CODEC Clock Output CODEC_BCLK I/O CODEC Digital Audio Bit Clock ...
Page 16
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C CODEC OPERATION This section describes various operating modes for the CODEC. CODEC RESETTING The CODEC contains a power-on reset circuit that resets the internal state of the device to a known condition. The power-on reset is applied as V powers on and released only after the ...
Page 17
... DACLRC/ ADCLRC BCLK DACDAT ADCDAT MSB ADSP-BF523C/ADSP-BF525C/ADSP-BF527C 2 • I • Frame Sync mode These are shown in Page 19. See information. These modes operate with 16-bit to 32-bit data except that 32-bit data is not supported in right justified mode. All four of these modes are MSB first. ...
Page 18
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C I2S Mode mode is where the MSB is available on the second rising edge of CODEC_BCLK following a DACLRC or ADCLRC transition. LEFT CHANNEL DACLRC/ ADCLRC CODEC_BCLK 1 CODEC_BCLK DACDAT ADCDAT MSB Right Justified Mode Right justified mode is where the LSB is available on the rising edge of CODEC_BCLK preceding a DACLRC or ADCLRC transition, yet MSB is still transmitted first ...
Page 19
... In slave mode the DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio. The CODEC_BCLK input need not be continuous however required that there are sufficient CODEC_BCLK cycles for each DACLRC/ADCLRC transition to clock the chosen data word length. The non 50:50 requirement on the LRCs is useful in situ- ADSP-BF523C/ADSP-BF525C/ADSP-BF527C 1/f S RIGHT CHANNEL n-2 n ...
Page 20
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Mode Configuration The ADC and DAC digital audio interface modes are software configurable as indicated in Table 14. Dynamically changing the software format may result in erroneous operation of the inter- faces and is therefore not recommended. Table 14. Digital Audio Interface Control Register Bit Label Default Description ...
Page 21
... CODEC DACLRC ADCDAT DACDAT OTE: ADC AND DAC CAN RUN AT DIFFERENT RATES Figure 25. Slave Mode ADSP-BF523C/ADSP-BF525C/ADSP-BF527C AUDIO DATA SAMPLING RATES The CODEC provides for two modes of operation (normal and USB) to generate the required DAC and ADC sampling rates. Use Table 16 Table 16. Sample Rate Control Table 15 ...
Page 22
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C and 48 kHz respectively, then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 for a 12.288 MHz CODEC_MCLK; or with BOSR = 1, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 for a 18.432 MHz CODEC_MCLK. The ADC and DAC will operate with a digital filter of type 1. See Digital Filter Characteristics on Page 39 the different filter types ...
Page 23
... Table 20 can be used to set up the device to work with various sample rate combinations. For example if the ADC and DAC sample rates are 48 kHz and 48 kHz then the CODEC should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Table 18. Actual Sampling Rate 8.01 kHz 8 kHz (11.2896 MHz/256) × ...
Page 24
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C The actual sample rates achieved are shown in Table 20. USB Mode Sample Rate Look-up Sampling Rate CODEC_MCLK Sample Rate Register (kHz) Frequency Setting (MHz) ADC DAC BOSR SR3 SR2 SR1 SR0 48 48 12.000 0 44.118 44.118 12.000 1 48 8.021 12.000 0 44.118 8.021 12 ...
Page 25
... Each write to a register requires the complete sequence of start condition, device address, and read/write bit followed by the 16-bit register address and data. ADSP-BF523C/ADSP-BF525C/ADSP-BF527C has one of two slave addresses that are selected by setting the state of pin 15, (CSB). The TWI interface protocol is shown in Figure 26 ...
Page 26
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C The power down control can be used to permanently disable functions when not required in certain applications. Or the modes can be used to dynamically power functions up and down depending on the operating mode, for example during playback or record. If dynamic implementations are used, the special instructions in the following sections should be followed. ...
Page 27
... RINMUTE 8 RLINBOTH Register 2 6:0 LHPVOL 000 0010 [6:0] Left Headphone Out 7 LZCEN 8 LRHPBOTH ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Table 28. The detailed 16-bits per register (7-bit address plus nine bits of data). These and in the rele- can be controlled using either the two wire USB or three wire SPI interface ...
Page 28
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Table 29. Register Descriptions (Continued) Register Address Bit Label Register 3 6:0 RHPVOL 000 0011 [6:0] Right Headphone Out 7 RZCEN 8 RLHPBOTH Register 4 0 MICBOOST 000 0100 Analog Audio Path Control 1 MUTEMIC 2 INSEL 3 BYPASS 4 DACSEL 5 SIDETONE 7:6 SIDEATT[1:0] 00 Register 5 0 ADCHPD 000 0101 Digital Audio Path Control ...
Page 29
... POWEROFF 1 Register 7 1:0 FORMAT[1:0] 10 000 0111 Digital Audio Interface Format 3:2 IWL[1:0] 4 LRP 5 LRSWAP BCLKINV ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Default Description 1 Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down 1 Microphone Input and Bias Power Down 1 = Enable Power Down 0 = Disable Power Down 1 ADC Power Down ...
Page 30
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Table 29. Register Descriptions (Continued) Register Address Bit Label Register 8 0 USB/ 000 1000 NORMAL Sampling Control 1 BOSR 5:2 SR[3:0] 6 CLKIDIV2 7 CLKODIV2 Register 9 0 ACTIVE 000 1001 Active Control Register 10 8:0 RESET 000 1111 Reset Register Default Description 0 Mode Select 1 = USB Mode (250/272 × f ...
Page 31
... BF527 Revision PrD datasheet for the additional current consumption of the Blackfin processor. 2 AVDD, HPVDD 1.8V, AGND = 0V, T DDEXT 3 All values are quiescent, with no signal. 4 All values are measured with the audio interface in master mode (MS = 1). 5 The power dissipation in the headphone itself is not included in this table. ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Conditions ...
Page 32
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C ELECTRICAL CHARACTERISTICS 1 Parameter Line Input to ADC SNR Signal to Noise Ratio SNR Signal to Noise Ratio DR Dynamic Range THD Total Harmonic Distortion –1 dB Input Gain Microphone Input to ADC SNR Signal to Noise Ratio DR Dynamic Range THD Total Harmonic Distortion 0 dB Input Gain ...
Page 33
... Figure 28. Product Information on Package Table 31. Package Brand Information Brand Key Field Description t Temperature Range pp Package Type Z Lead Free Option ccc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision yyww Date Code ADSP-BF523C/ADSP-BF525C/ADSP-BF527C and Table 31 provides Rev. PrC | Page June 2008 ...
Page 34
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C CODEC CLOCK TIMING XTI/CODEC_MCLK Table 32. CODEC Clock Timing Requirements Parameter t XTI/CODEC_MCLK System clock pulse width high XTIH t XTI/CODEC_MCLK System clock pulse width low XTIL t XTI/CODEC_MCLK System clock cycle time XTIY XTI/CODEC_MCLK Duty cycle 1 AVDD, HPVDD 3.3 V, AGND = DDEXT XTI/CODEC_MCLK CODEC_CLKOUT CODEC_CLKOUT ÷ ...
Page 35
... DACDAT setup time to CODEC_BCLK rising edge DST t DACDAT hold time from CODEC_BCLK rising edge DHT 1 AVDD, HPVDD 3.3 V, AGND = DDEXT ADSP-BF523C/ADSP-BF525C/ADSP-BF527C t t DST DHT Figure 31. Digital Audio Data Timing—Master Mode Test Conditions = +25°C, Slave Mode kHz, XTI/CODEC_MCLK = 256 × f ...
Page 36
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C DIGITAL AUDIO INTERFACE—SLAVE MODE t BCH CODEC_BCLK DACLRC/ ADCLRC DACDAT ADCDAT Table 35. Digital Audio Data Timing—Slave Mode Parameter t CODEC_BCLK cycle time BCY t CODEC_BCLK pulse width high BCH t CODEC_BCLK pulse width low BCL t DACLRC/ADCLRC set-up time to CODEC_BCLK rising LRSU edge ...
Page 37
... CSB pulse width low CSL t CSB pulse width high CSH t CSB rising to CSCL rising CSS 1 AVDD, HPVDD 3.3 V, AGND = DDEXT ADSP-BF523C/ADSP-BF525C/ADSP-BF527C t CSL t SCY t SCH t SCL t DSU t DHO Figure 33. Program Register Input Timing—SPI Serial Control Mode 1 Test Conditions o = +25 C, Slave Mode kHz, XTI/CODEC_MCLK = 256 × ...
Page 38
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C t 3 CSDA t 6 CSCL t 1 Table 37. Program Register Input Timing—TWI Serial Control Mode Parameter CSCL Frequency t1 CSCL Low Pulsewidth t2 CSCL High Pulsewidth t3 Hold Time (Start Condition) t4 Setup Time (Start Condition) t5 Data Setup Time t6 CSDA, CSCL Rise Time t7 CSDA, CSCL Fall Time ...
Page 39
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C The ADC and DAC employ different digital filters. There are four types of digital filter, called Type and 3. The perfor- mance of Types 0 and 1 is listed in filters is shown in the proceeding pages ADC Filters 12 ÷ ...
Page 40
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C 289-BALL MINI-BGA PINOUT Table 40 lists the mini-BGA pinout by signal mnemonic. Table 41 on Page 42 lists the mini-BGA pinout by ball number. Table 40. 289-Ball Mini-BGA Ball Assignment (Alphabetically by Signal) Signal Ball Signal Ball No. No. ABE0/SDQM0 AB9 CSB D23 ABE1/SDQM1 AC9 CSCL B23 ADCDAT ...
Page 41
... CODEC_CLKOUT D22 GND L9 CLKBUF AB19 GND L10 CLKIN R23 GND L11 CLKOUT AB18 GND L12 CMODE E22 GND L13 ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Signal Ball Signal Ball Signal No. No. MICIN J23 PH10 M22 VDDEXT NMI U22 PH11 R22 VDDEXT VPPOTP AB11 PH12 M23 VDDEXT ...
Page 42
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Table 41. 289-Ball Mini-BGA Ball Assignment (Numerically by Ball Number) Ball Signal Ball Signal No. No. A1 GND B23 CSCL A2 PG12 C1 PG8 A3 PG13 C2 PG6 A4 PG14 C22 SDA A5 PG15 C23 CSDA A6 PPICLK/TMRCLK D1 PG4 A7 PF0 D2 PG5 A8 PF2 D22 CODEC_CLKOUT J10 GND A9 PF14 D23 CSB A10 PF15 ...
Page 43
... A1 BALL PAD CORNER KEY: V GND AGND DDINT V I/O V DDEXT DDMEM AVDD HPVDD HPGND ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Ball Signal Ball Signal Ball No. No. No. L13 GND P13 GND U13 VDDMEM AB23 USB_XI L14 GND P14 GND U14 VDDMEM AC1 L15 GND P15 GND ...
Page 44
... ADSP-BF523C/ADSP-BF525C/ADSP-BF527C ORDERING GUIDE Temperature 1 Model Range ADSP-BF527KBCZ6C1X 0ºC to +70ºC 289-Ball Chip Scale Package Ball Grid Array 1 Referenced temperature is ambient temperature. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...