ADSP-BF523C AD [Analog Devices], ADSP-BF523C Datasheet - Page 34

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ADSP-BF523C

Manufacturer Part Number
ADSP-BF523C
Description
Blackfin Embedded Processor 289-ball MBGA package
Manufacturer
AD [Analog Devices]
Datasheet
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
CODEC CLOCK TIMING
Table 32. CODEC Clock Timing Requirements
1
Table 33. Clock Out Timing Requirements
1
Parameter
t
t
t
Parameter
t
AVDD, HPVDD, V
AVDD, HPVDD, V
XTIH
XTIL
XTIY
COP
XTI/CODEC_MCLK
CODEC_CLKOUT
CODEC_CLKOUT ÷ 2
CODEC_CLKOUT propagation delay from
XTI/CODEC_MCLK falling edge
XTI/CODEC_MCLK System clock pulse width high
XTI/CODEC_MCLK System clock pulse width low
XTI/CODEC_MCLK System clock cycle time
XTI/CODEC_MCLK Duty cycle
XTI/CODEC_MCLK
DDEXT
DDEXT
= 3.3 V, AGND = 0 V, T
= 3.3V, AGND = 0V, T
A
A
= +25°C, Slave Mode, f
= +25°C, Slave Mode f
Figure 30. CODEC_CLKOUT Timing Requirements
t XTIL
Figure 29. CODEC Clock Timing Requirements
Rev. PrC | Page 34 of 44 | June 2008
t XTIY
t XTIH
S
s
= 48 kHz, XTI/CODEC_MCLK = 256 × f
= 48 kHz, XTI/CODEC_MCLK = 256 × f
Test Conditions
t
COP
1
Test Conditions
S
Preliminary Technical Data
s
unless otherwise stated.
unless otherwise stated.
1
Min
18
18
54
40:60
Min Typical Max Unit
0
Typical Max Unit
60:40
10
ns
ns
ns
ns

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