ADSP-BF523C AD [Analog Devices], ADSP-BF523C Datasheet - Page 23

• Manufacturer Part Number: ADSP-BF523C
• Description: Blackfin Embedded Processor 289-ball MBGA package
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
The actual sample rates achieved are shown in
Table 18. Normal Mode Actual Sample Rates
128/192 × fS Normal Mode
The normal mode sample rates are designed for standard
256 × f
also be clocked from a 128 × f
the limited sampling rates shown in
Table 19. 128 × f
512/768×fS Normal Mode
512 × f
dated by using the CLKIDIV2 bit (register 8, bit 6). See
on Page 21
divided by two so an external 512/768 × f
become 256/384 × f
as in
specified rate.
USB Mode Sample Rates
In USB mode the CODEC_MCLK/crystal oscillator input is 12
MHz only.
Table 20
sample rate combinations. For example if the ADC and DAC
sample rates are 48 kHz and 48 kHz then the CODEC should be
programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and
Target
Sampling
Rate
8 kHz
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
Sampling
Rate (kHz)
ADC DAC
48
44.1 44.1 5.6448 MHz
Table 17 on Page 22
48
S
S
and 384 × f
and 768 × f
can be used to set up the device to work with various
for software control. The CODEC clock will be
n/a
n/a
CODEC_MCLK = 12.288 MHz CODEC_MCLK = 11.2896 MHz CODEC_MCLK = 18.432 MHz CODEC_MCLK = 16.9344 MHz
8 kHz
(12.288 MHz/256) × 1/6
32 kHz
(12.288 MHz/256) × 2/3
48 kHz
12.288 MHz/256
96 kHz
(12.288 MHz/256) × 2
CODEC_MCLK
Frequency
6.144 MHz
9.216 MHz
8.4672 MHz
S
Normal Mode Sample Rate Look-up
S
S
S
CODEC_MCLK rates. The CODEC can
CODEC_MCLK rates can be accommo-
internally. The CODEC otherwise operates
but with CODEC_MCLK at twice the
Sample Rate Register
Setting
BOSR SR3 SR2 SR1 SR0
0
1
0
1
S
or 192 × f
Table
0
0
1
1
BOSR = 0
S
S
1
1
1
1
CODEC_MCLK for
19.
CODEC_MCLK will
8.01 kHz
(11.2896 MHz/256) × 2/11
n/a
44.1 kHz
11.2896 MHz/256
n/a
88.2 kHz
(11.2896 MHz/256) × 2
n/a
Table
1
1
1
1
Rev. PrC | Page 23 of 44 | June 2008
1
1
1
1
18.
Table 16
Digital
Filter
Type
2
2
2
2
Actual Sampling Rate
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
SR0 = 0. The ADC and DAC then operate with a digital filter of
type 0. See
nation of the different filter types.
The BOSR bit represents the base over-sampling rate. This is the
rate at which the CODEC digital signal processing is carried out.
The sampling rate will always be a sub-multiple of the base over-
sampling rate. In USB mode, with BOSR = 0, the base over-sam-
pling rate is 250 × f
rate is 272 × f
sampling rate produced by the ADC and required by the DAC.
Examples
8 kHz
(18.432 MHz/384) × 1/6
32 kHz
(18.432 MHz/384) × 2/3
n/a
48 kHz
18.432 MHz/384
n/a
96 kHz
(18.432 MHz/384) × 2
1. With ADC data sampling rate 8 kHz and DAC data sam-
2. With ADC data rate 8 kHz and DAC data rate 44.1 kHz—
pling rate 48 kHz—program the device with BOSR = 0
(256 × f
be exactly 8 kHz ((12 MHz/250)
expects data at exactly 48 kHz (12 MHz/250).
program the device with BOSR = 1 (272 × f
SR2 = 0, SR1 = 1, SR0 = 0. The ADC will output data at
8.021 kHz ((12 MHz/272)
and the DAC will be 44.118 kHz (12 MHz/272). A slight
(sub 0.5%) pitch shift occurs in the 8 kHz and 44.1 kHz
audio data and (importantly) the user must ensure that the
data across the digital interface is correctly synchronized at
the 8.021 kHz and 44.117 kHz rates.
Digital Filter Characteristics on Page 39
S
), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will
S
. This can be used to determine the actual audio
S
. With BOSR = 1, the base over-sampling
BOSR = 1
×
8.018 kHz
(16.9344 MHz/384) × 2/11
n/a
44.1 kHz
16.9344 MHz/384
n/a
88.2 kHz
(16.9344 MHz/384) × 2
n/a
2/11) instead of exactly 8 kHz
×
1/6) and the DAC
S
), SR3 = 1,
for an expla-