ADSP-BF523C AD [Analog Devices], ADSP-BF523C Datasheet - Page 17

• Manufacturer Part Number: ADSP-BF523C
• Description: Blackfin Embedded Processor 289-ball MBGA package
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
there is more than one master clock available, it is recom-
mended that the clock be generated by the CODEC to maximize
performance.
CODEC_CLKOUT
The CODEC clock is available to the external audio system on
the CODEC_CLKOUT pin. The CODEC clock is buffered for
driving external loads. There is no phase inversion between
XTI/CODEC_MCLK, the CODEC clock and
CODEC_CLKOUT but there will inevitably be some delay. The
delay will be dependent on the load that CODEC_CLKOUT
drives. See
CODEC_CLKOUT can also be divided by two. See
the software control.
CODEC_CLKOUT is disabled and set low whenever the device
is in reset.
Table 13. Programming CODEC_CLKOUT
If CODEC_CLKOUT is not needed, the CODEC_CLKOUT
buffer on the CODEC can be safely powered down to conserve
power (see
has a choice, f
conserve power. CODEC_CLKOUT changes on the rising edge
of CODEC_MCLK when f
DIGITAL AUDIO INTERFACES
The CODEC accommodates four digital audio interface
formats.
Register
Address
000 1000 7
DACLRC/
ADCLRC
DACDAT/
ADCDAT
• Right justified
• Left justified
BCLK
Electrical Characteristics on Page
Bit Label
Power Down Modes on Page
CODEC_CLKOUT
CLKODIV2 0
MSB
1
2
Default Description
CODEC_MCLK
= f
3
CODEC_MCLK
LEFT CHANNEL
CODEC Clock Divider Select
1 = CODEC_CLKOUT is
CODEC Clock ÷ 2
0 = CODEC_CLKOUT is
CODEC Clock
/2 is selected.
25). If the programmer
/2 is recommended to
n-2 n-1
32.
n
Table 13
Rev. PrC | Page 17 of 44 | June 2008
LSB
Figure 19. Left Justified Mode
for
MSB
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
1/f
S
1
2
These are shown in
Page
information. These modes operate with 16-bit to 32-bit data
except that 32-bit data is not supported in right justified mode.
All four of these modes are MSB first.
The digital audio interface takes the data from the internal ADC
digital filter and places it on the ADCDAT output. ADCDAT is
the formatted digital audio data stream output from the ADC
digital filters with left and right channels multiplexed together.
ADCLRC is an alignment clock that controls whether left or
right channel data is present on the ADCDAT lines. ADCDAT
and ADCLRC are synchronous with the CODEC_BCLK signal,
with each data bit transition signified by a CODEC_BCLK high-
to-low transition. CODEC_BCLK can be an input or an output
depending on whether the device is in master or slave mode. See
Master and Slave Mode Operation on Page
The digital audio interface also receives the digital audio data
for the internal DAC digital filters on the DACDAT input.
DACDAT is the formatted digital audio data stream output to
the DAC digital filters with left and right channels multiplexed
together. DACLRC is an alignment clock that controls whether
left or right channel data is present on DACDAT. DACDAT
and DACLRC are synchronous with the CODEC_BCLK signal
with each data bit transition signified by a CODEC_BCLK high-
to-low transition. DACDAT is always an input. CODEC_BCLK
and DACLRC are either outputs or inputs depending whether
the CODEC is in master or slave mode. See
Mode Operation on Page
In all modes DACLRC and ADCLRC must always change on
the falling edge of CODEC_BCLK.
Left Justified Mode
Left justified mode is where the MSB is available on the first ris-
ing edge of CODEC_BCLK following a ADCLRC or DACLRC
transition.
3
• I
• Frame Sync mode
19. See
2
S
RIGHT CHANNEL
Electrical Characteristics on Page 32
n-2 n-1
Figure 19 on Page 17
n
LSB
21.
to
21.
Master and Slave
Figure 23 on
for timing