ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet
ADSP-BF561_06
Related parts for ADSP-BF561_06
ADSP-BF561_06 Summary of contents
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... CONTROLLER2 32 DAB PPI0 PPI1 Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ® Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 2 S channels -compatible port ® IRQ CONTROL/ WATCHDOG TIMER L1 L2 SRAM DATA 128K BYTES MEMORY IMDMA ...
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... ADSP-BF561 TABLE OF CONTENTS General Description ................................................. 4 Portable Low Power Architecture ............................. 4 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers .................................................. 9 Watchdog Timer .................................................. 9 Timers ............................................................. 10 Serial Ports (SPORTs) .......................................... 10 Serial Peripheral Interface (SPI) Port ....................... 10 UART Port ........................................................ 10 Programmable Flags (PFx) .................................... 11 Parallel Peripheral Interface ................................... 11 Dynamic Power Management ................................ 12 Voltage Regulation .............................................. 13 Clock Signals ..................................................... 13 Booting Modes ...
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... Figure 44.................. 44 Reordered Table 36 .................................................. 46 Added Table 37....................................................... 48 Added Figure 47 and Figure 48 ................................... 50 Added Figure 45 and Figure 46 ................................... 50 Reordered Table 38 .................................................. 51 Added Table 39....................................................... 53 Added Section for Surface Mount Design ...................... 57 Changed Ordering Guide .......................................... 58 1/05—Initial version Rev Page May 2006 ADSP-BF561 ...
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... RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capa- bilities in a single instruction set architecture. The ADSP-BF561 processor has 328K bytes of on-chip memory. Each Blackfin core includes: • 16K bytes of instruction SRAM/cache • 16K bytes of instruction SRAM • ...
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... R1.H R0.H R0.L MEMORY ARCHITECTURE The ADSP-BF561 views memory as a single unified 4G byte address space, using 32-bit addresses. All resources including internal memory, external memory, and I/O control registers occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierar- ...
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... Mapped Registers (MMRs) but share the same system MMR registers and 128K bytes L2 SRAM memory. External (Off-Chip) Memory The ADSP-BF561 external memory is accessed via the External Bus Interface Unit (EBIU). This interface provides a glueless connection four banks of synchronous DRAM CORE A MEMORY MAP ...
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... When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF561 event controller consists of two stages: the Core Event Controller (CEC) and the System Interrupt Control- ler (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events ...
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... Supplemental Interrupt 1 IVG8 Event Control IVG9 IVG9 The ADSP-BF561 provides the user with a very flexible mecha- nism to control the processing of events. In the CEC, three IVG9 registers are used to coordinate and control events. Each of the IVG9 registers is 16 bits wide, while each bit represents a particular IVG9 event class ...
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... DMA (IMDMA) Controller. The IMDMA Controller allows data transfers between any of the internal L1 and L2 memories. WATCHDOG TIMER Each ADSP-BF561 core includes a 32-bit timer, which can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the proces- sor to a known state, via generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software ...
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... The timer is clocked by the system clock (SCLK maximum frequency SCLK TIMERS There are 14 programmable timer units in the ADSP-BF561. Each of the 12 general-purpose timer units can be indepen- dently programmed as a Pulse-Width Modulator (PWM), internally or externally clocked timer, or pulse-width counter. The general-purpose timer units can be used in conjunction ...
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... Flag Control and Status Registers – Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF561 employs a “write one to set” and “write one to clear” mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags ...
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... The use of multiple power domains maximizes flexibility, while maintaining compliance with industry stan- dards and conventions. By isolating the internal logic of the ADSP-BF561 into its own power domain, separate from the I/O, the processor can take advantage of Dynamic Power Manage- ment, without affecting the I/O devices. There are no sequencing requirements for the various power domains ...
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... OUT AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. Figure 4. Voltage Regulator Circuit CLOCK SIGNALS The ADSP-BF561 can be clocked by an external crystal, a sine wave input buffered, shaped clock derived from an external clock oscillator external clock is used, it should be a TTL-compatible signal ...
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... MSEL value are changed. The time base for the PLL_LOCKCNT register is the period of CLKIN. BOOTING MODES The ADSP-BF561 has three mechanisms (listed in automatically loading internal L1 instruction memory or L2 after a reset. A fourth mode is provided to execute from external memory, bypassing the boot sequence. ...
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... Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded as 16-bits. DEVELOPMENT TOOLS The ADSP-BF561 is supported with a complete set of ®† CROSSCORE software and hardware development tools, including Analog Devices emulators and the VisualDSP++ development environment ...
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... Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF561 to monitor and control the target board processor during emulation. The emulator provides full- speed emulation, allowing inspection and modification of mem- ory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’ ...
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... PIN DESCRIPTIONS ADSP-BF561 pin definitions are listed in inputs should be tied or pulled to V DDEXT currents for each driver type are shown in Figure 33. Table 8. Pin Descriptions Pin Name Type Function EBIU ADDR25–2 O Address Bus for Async/Sync Access DATA31–0 I/O Data Bus for Async/Sync Access ABE3– ...
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... ADSP-BF561 Table 8. Pin Descriptions (Continued) Pin Name Type Function PPI0 PPI0D15–8/PF47–40 I/O PPI Data/Programmable Flag Pins PPI0D7–0 I/O PPI Data Pins PPI0CLK I PPI Clock PPI0SYNC1/TMR8 I/O PPI Sync/Timer PPI0SYNC2/TMR9 I/O PPI Sync/Timer PPI0SYNC3 I/O PPI Sync PPI1 PPI1D15–8/PF39–32 I/O PPI Data/Programmable Flag Pins PPI1D7– ...
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... GND G Power Supply Return No Connection Refer to Figure 27 on Page 41 to Figure 31 on Page 42. Rev Page May 2006 ADSP-BF561 Driver 1 Type Pull-Up/Down Requirement C None Internal Pull-down C None Internal Pull-down Internal Pull-down External Pull-down Necessary If JTAG Not Used Needs Level or Clocking ...
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... ADSP-BF561SBB600 –7% to +12% DDINT 3 Internal voltage regulator tolerance: ADSP-BF561SBB500 –7% to +12% except at 1. DDINT 4 The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum V approximately equals V (maximum). This 3.3 V tolerance applies to bidirectional and input only pins. DDEXT 5 Applies to all signal pins. ELECTRICAL CHARACTERISTICS Parameter V ...
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... CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF561 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfor- mance degradation or loss of functionality ...
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... Table 11 through Table 13 describe the timing requirements for the ADSP-BF561 clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock, and Voltage Controlled Oscillator (VCO) operat- Table 11. Core Clock Requirements—ADSP-BF561SKBCZ500, ADSP-BF561SKB500, ADSP-BF561SKBZ500, ...
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... CLKIN (not including startup time of external clock oscillator). t CKIN CLKIN t CKINL RESET 3 period is 50 ns. CKIN t CKINH t WRST Figure 8. Clock and Reset Timing Rev Page May 2006 ADSP-BF561 Min Max 1 25.0 100.0 10.0 10 CKIN Unit ...
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... ADSP-BF561 Asynchronous Memory Read Cycle Timing Table 17. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements t DATA31–0 Setup Before CLKOUT SDAT t DATA31–0 Hold After CLKOUT HDAT t ARDY Setup Before CLKOUT SARDY t ARDY Hold After CLKOUT HARDY Switching Characteristics t Output Delay After CLKOUT ...
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... ARDY t END AT DATA31–0 WRITE DATA 1 1 ACCESS PROGRAMMED WRITE HOLD EXTENDED ACCESS 2 CYCLES 1 CYCLE 1 CYCLE HARDY SARDY t SARDY Figure 10. Asynchronous Memory Write Cycle Timing Rev Page May 2006 ADSP-BF561 Min Max 4.0 0.0 6.0 1.0 6.0 0 Unit ...
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... ADSP-BF561 SDRAM Interface Timing Table 19. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before CLKOUT SSDAT t DATA Hold After CLKOUT HSDAT Switching Characteristics 1 t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL t Command, ADDR, Data Delay After CLKOUT ...
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... The pad loads for these timing parameters are 20 pF. CLKOUT AMSx ADDR25-2 ABE3-0 AWE ARE BG BGH Figure 12. External Port Bus Request and Grant Cycle Timing Rev Page May 2006 ADSP-BF561 Min Max 4.6 0.0 4.5 4.5 3.6 3.6 3.6 3 DBG t EBG t ...
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... ADSP-BF561 Parallel Peripheral Interface Timing Table 21, and Figure 13 through Figure 16 Peripheral Interface operations. Table 21. Parallel Peripheral Interface Timing Parameter Timing Requirements 1 t PPI_CLK Width PCLKW 1 t PPI_CLK Period PCLK t External Frame Sync Setup Before PPI_CLK SFSPE t External Frame Sync Hold After PPI_CLK ...
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... FOR DATA1 IS DATA0 SAMPLED t HFSPE t SFSPE t HDRPE Figure 14. PPI GP Rx Mode with External Frame Sync Timing FRAME DATA0 IS SYNC IS DRIVEN SAMPLED OUT t HFSPE t HDTPE DATA0 t DDTPE Figure 15. PPI GP Tx Mode with External Frame Sync Timing Rev Page May 2006 ADSP-BF561 ...
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... ADSP-BF561 FRAME SYNC IS DRIVEN OUT PPI_CLK POLC = 0 PPI_CLK POLC = 1 t DFSPE t HOFSPE POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA DATA0 IS DRIVEN OUT t DDTPE t HDTPE DATA0 Figure 16. PPI GP Tx Mode with Internal Frame Sync Timing Rev Page May 2006 ...
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... Data Enable Delay from Internal TSCLK DTENI t Data Disable Delay from Internal TSCLK DDTTI 1 Referenced to drive edge. and Figure 17 describe Serial Port Rev Page May 2006 ADSP-BF561 Min Max 3.0 3.0 3.0 3.0 4.5 15.0 10.0 0.0 10.0 0.0 Min Max 8.0 –2.0 6.0 0.0 4.5 15.0 3.0 –1.0 3.0 –2.0 4 ...
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... ADSP-BF561 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW RSCLK t DFSE t t HOFSE SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE t SCLKIW TSCLK t DFSI t t HOFSI ...
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... BIT t DDTLFSE DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I t DTENLFS t HDTE/I 1ST BIT t DDTLFSE Figure 18. External Late Frame Sync (Frame Sync Setup < t Rev Page May 2006 ADSP-BF561 Min Max 10.0 0 and t apply. DTENLFS 2ND BIT 2ND BIT /2) SCLK Unit ns ns ...
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... ADSP-BF561 EXTERNAL RFS WITH MCE = 1, MFD = 0 RSCLK RFS DT LATE EXTERNAL TFS TSCLK TFS DT DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE/I t DTENLSCK t HDTE/I 1ST BIT t DDTLSCK DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE/I t DTENLSCK t HDTE/I 1ST BIT t DDTLSCK Figure 19. External Late Frame Sync (Frame Sync Setup > t Rev ...
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... SPICHM t t DDSPIDM HDSPIDM MSB t t HSPIDM SSPIDM MSB VALID t DDSPIDM MSB t HSPIDM LSB VALID Figure 20. Serial Peripheral Interface (SPI) Port—Master Timing Rev Page May 2006 ADSP-BF561 Min Max 7.5 –1.5 2t –1.5 SCLK 2t –0.5 SCLK 2t –1.5 SCLK 4t –1.5 SCLK 2t –1.5 ...
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... ADSP-BF561 Serial Peripheral Interface (SPI) Port— Slave Timing Table 27 and Figure 21 describe SPI port slave operations. Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period ...
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... UART TRANSMIT INTERRUPT Figure 22, DATA8–5 START DATA8–5 Figure 22. UART Port—Receive and Transmit Timing Rev Page May 2006 ADSP-BF561 STOP UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ STOP2–1 UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT ...
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... ADSP-BF561 Programmable Flags Cycle Timing Table 28 and Figure 23 describe programmable flag operations. Table 28. Programmable Flags Cycle Timing Parameter Timing Requirement t Flag Input Pulse Width WFI Switching Characteristic t Flag Output Delay from CLKOUT Low DFO CLKOUT PF (OUTPUT) PF (INPUT) t DFO FLAG OUTPUT t WFI FLAG INPUT Figure 23 ...
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... HTO CLKOUT TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES) 32 equals (2 –1) cycles. HTO t HTO Figure 24. Timer PWM_OUT Cycle Timing Rev Page May 2006 ADSP-BF561 Min Max Unit 1 SCLK 1 SCLK –1) SCLK ...
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... ADSP-BF561 JTAG Test and Emulation Port Timing Table 30 and Figure 25 describe JTAG port operations. Table 30. JTAG Port Timing Parameter Timing Parameters t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... OUTPUT DRIVE CURRENTS Figure 26 through Figure 33 show typical current voltage char- acteristics for the output drivers of the ADSP-BF561 processor. The curves represent the current drive capability of the output drivers as a function of output voltage. Refer to Page 17 to identify the driver type for a pin. ...
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... Manual for definitions of the various operating modes and for instructions on how to minimize system power Many operating conditions can affect power dissipation. System designers should refer to EE-293: Estimating Power for ADSP- V BF561 Blackfin Processors on the Analog Devices website OL (www.analog.com)—use site search on “EE-293.” This docu- ment provides detailed information for optimizing your design for lowest power ...
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... Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate t Figure the difference between the ADSP-BF561 processor’s out- put voltage and the input threshold for the device requiring the is 1.5 V for MEAS hold time. C the total leakage or three-state current (per data line) ...
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... ADSP-BF561 ABE_B[0] (133 MHz DRIVER), V (MIN) = 2.25V, TEMPERATURE = 85°C DDEXT 14 12 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 37. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver (min) DDEXT ABE0 (133 MHz DRIVER), V (MAX) = 3.65V, TEMPERATURE = 85°C ...
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... Table 34. Thermal Characteristics for BC-256 Package Parameter JA JMA JMA Table 35. Thermal Characteristics for B-297 Package Parameter JA JMA JMA Rev Page May 2006 ADSP-BF561 = + CASE case temperature ( C) measured by customer at top Table 34 and Table 35. Power Dissipation on Page 42 ). ...
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... ADSP-BF561 256-BALL MBGA PINOUT Table 36 lists the 256-Ball MBGA pinout by ball number. Table 37 on Page 48 lists the 256-Ball MBGA pinout alphabeti- cally by signal. Table 36. 256-Ball MBGA Pin Assignment (Numerically by Ball Number) Ball No. Signal Ball No. Signal A01 VDDEXT C09 SMS2 A02 ADDR24 ...
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... PF10 T03 R08 PF14 T04 R09 NMI1 T05 R10 TDI T06 R11 EMU T07 R12 MISO T08 Rev Page May 2006 ADSP-BF561 Ball No. Signal TX/PF26 T09 TCK TSCLK1/PF31 T10 TMS DT1PRI/PF23 T11 SLEEP RFS0/PF19 T12 VDDEXT VDDEXT T13 RX/PF27 PPI1D4 ...
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... ADSP-BF561 Table 37. 256-Ball MBGA Pin Assignment (Alphabetically by Signal) Signal Ball No. Signal ABE0/SDQM0 E11 BR ABE1/SDQM1 B13 BYPASS ABE2/SDQM2 A14 CLKIN ABE3/SDQM3 A15 DATA0 ADDR02 D13 DATA1 ADDR03 G11 DATA2 ADDR04 B15 DATA3 ADDR05 G10 DATA4 ADDR06 B14 DATA5 ADDR07 C14 DATA6 ADDR08 ...
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... VDDEXT G16 A10 VDDEXT J06 C10 VDDEXT K06 E10 VDDEXT K16 T09 VDDEXT L05 R10 VDDEXT L10 Rev Page May 2006 ADSP-BF561 Signal Ball No. VDDEXT M14 VDDEXT T01 VDDEXT T03 VDDEXT T06 VDDEXT T08 VDDEXT T12 VDDEXT T16 VDDINT E08 ...
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... ADSP-BF561 Figure 45 lists the top view of the 256-Ball MBGA ball configu- ration. Figure 46 lists the bottom view of the 256-Ball MBGA ball configuration. A1 BALL PAD CORNER TOP VIEW Figure 45. 256-Ball MBGA Ball Configuration (Top View) ...
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... DATA0 L01 NC DATA3 L02 NC PPI0D13/PF45 L10 VDDEXT PPI0D12/PF44 L11 GND DATA2 L12 GND DATA5 L13 GND Rev Page May 2006 ADSP-BF561 Ball No. Signal L14 GND L15 GND L16 GND L17 GND L18 VDDINT L25 DATA12 L26 DATA15 M01 VROUT0 M02 ...
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... ADSP-BF561 Table 38. 297-Ball PBGA Pin Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. P15 GND U11 P16 GND U12 P17 GND U13 P18 VDDINT U14 P25 DATA18 U15 P26 DATA21 U16 R01 PPI0D5 U17 R02 PPI0D6 U18 R10 VDDEXT U25 R11 ...
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... W25 DATA29 V26 DATA30 Y25 DATA31 W26 DR0PRI AB26 DR0SEC/PF20 AC25 DR1PRI AF22 DR1SEC/PF25 AE23 DT0PRI/PF18 Y26 Rev Page May 2006 ADSP-BF561 Signal Ball No. Signal DT0SEC/PF17 AA25 GND DT1PRI/PF23 AF25 GND DT1SEC/PF22 AF24 GND EMU AE16 GND GND A01 GND ...
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... ADSP-BF561 Table 39. 297-Ball PBGA Pin Assignment (Alphabetically by Signal) (Continued) Signal Ball No. GND AF26 MISO AE19 MOSI AE20 NC K02 NC L01 NC L02 NC AD25 NC AE13 NC AE26 NMI0 AF18 NMI1 AF13 PF0/SPISS/TMR0 AE05 PF1/SPISEL1/TMR1 AF05 PF2/SPISEL2/TMR2 AE06 PF3/SPISEL3/TMR3 AF06 PF4/SPISEL4/TMR4 AE07 PF5/SPISEL5/TMR5 AF07 PF6/SPISEL6/TMR6 AE08 ...
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... Figure 47. 297-Ball PBGA Ball Configuration (Top View BOTTOM VIEW Figure 48. 297-Ball PBGA Ball Configuration (Bottom View) KEY: V DDINT GND V DDEXT I/O KEY: V DDINT V DDEXT Rev Page May 2006 ADSP-BF561 NC V ROUT GND NC I/O V ROUT ...
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... ADSP-BF561 OUTLINE DIMENSIONS Dimensions in the outline dimension figures are shown in millimeters. 12.00 BSC SQ A1 BALL PAD CORNER TOP VIEW 1.70 1.51 1.36 SIDE VIEW NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-225, WITH NO EXACT PACKAGE SIZE AND EXCEPTION TO PACKAGE HEIGHT. 3. MINIMUM BALL HEIGHT 0.25 9 ...
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... BOTTOM VIEW DETAIL A 0.20 MAX COPLANARITY 0.70 BALL DIAMETER 0.60 0.50 Figure 50. 297-Ball PBGA Grid Array (B-297) Ball Attach Type Solder Mask Opening Solder Mask Defined 0.30 mm diameter Solder Mask Defined 0.43 mm diameter Rev Page May 2006 ADSP-BF561 A1 BALL PAD CORNER 8. ...
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... ADSP-BF561SKBZ600 0°C to +70°C ADSP-BF561SBB600 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SBB500 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) 2 ADSP-BF561SBBZ600 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) 2 ADSP-BF561SBBZ500 – ...
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... Rev Page May 2006 ADSP-BF561 ...
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... ADSP-BF561 © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04696-0-5/06(A) Rev Page May 2006 ...