ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 33

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ADSP-BF561_06

Manufacturer Part Number
ADSP-BF561_06
Description
Blackfin Embedded Symmetric Multiprocessor
Manufacturer
AD [Analog Devices]
Datasheet
Table 25. External Late Frame Sync
1
2
Parameter
Switching Characteristics
t
t
MCE = 1, TFS enable and TFS valid follow t
If external RFS/TFS setup to RSCLK/TSCLK > t
DDTLFSE
DTENLFS
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
EXTERNAL RFS WITH MCE = 1, MFD = 0
LATE EXTERNAL TFS
RSCLK
RFS
DT
TSCLK
DT
TFS
DTENLFS
SCLKE
and t
/2, then t
Figure 18. External Late Frame Sync (Frame Sync Setup < t
DRIVE
DRIVE
DDTLFSE
t
t
t
DTENLFS
DTENLFS
t
DDTLFSE
DDTLFSE
.
DDTE
t
SFSE/I
t
SFSE/I
/
I
Rev. A | Page 33 of 60 | May 2006
and t
1, 2
SAMPLE
SAMPLE
DTENE
/
1ST BIT
1ST BIT
I
apply; otherwise t
DRIVE
DRIVE
t
t
HOFSE/I
t
DDTLFSE
HDTE/I
t
HOFSE/I
HDTE/I
t
DDTE/I
t
DDTE/I
1, 2
and t
DTENLFS
apply.
SCLK
2ND BIT
/2)
2ND BIT
Min
0
Max
10.0
ADSP-BF561
Unit
ns
ns

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