ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 23

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

Clock and Reset Timing
Table 16
Absolute Maximum Ratings on Page
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 600 MHz/133 MHz.
Table 16. Clock and Reset Timing
1
2
3
Parameter
Timing Requirements
t
t
t
t
If DF bit in PLL_CTL register is set, then the maximum t
Applies to bypass mode and nonbypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
CKIN
CKINL
CKINH
WRST
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
and
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
Figure 8
CLKIN
RESET
describe clock and reset operations. Per
2
2
t
CKINL
t
CKIN
21, combinations of
t
CKINH
3
CKIN
period is 50 ns.
Rev. A | Page 23 of 60 | May 2006
Figure 8. Clock and Reset Timing
t
WRST
Min
25.0
10.0
10.0
11 t
CKIN
Max
100.0
ADSP-BF561
1
Unit
ns
ns
ns
ns