ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
where the variables in the equations are:
The percent power savings is calculated as:
VOLTAGE REGULATION
The ADSP-BF561 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels 0.85 V to
1.25 V from an external 2.25 V to 3.6 V supply.
the typical external components required to complete the power
management system. The regulator controls the internal logic
voltage levels and is programmable with the Voltage Regulator
Control Register (VR_CTL) in increments of 50 mV. To reduce
standby power consumption, the internal voltage regulator can
be programmed to remove power to the processor core while
keeping I/O power (V
state V
buffers. The voltage regulator can be activated from this power-
down state by asserting RESET, which will then initiate a boot
sequence. The regulator can also be disabled and bypassed at the
user’s discretion.
VR
f
f
V
V
T
T
V
V
% power savings
OUT
CCLKNOM
CCLKRED
DDEXT
DDINT
NOM
RED
DDINTNOM
DDINTRED
DDEXT
1–0
is the duration running at f
power savings factor
is the duration running at f
can still be applied, eliminating the need for external
=
is the reduced core clock frequency
is the nominal core clock frequency
-------------------- -
f
NOTE: VR
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
f
is the reduced internal supply voltage
CCLKNOM
CCLKRED
is the nominal internal supply voltage
100µF
Figure 4. Voltage Regulator Circuit
100µF
OUT
1µF
DDEXT
=
1–0 SHOULD BE TIED TOGETHER EXTERNALLY
) supplied. While in the hibernate
⎛
⎝
1 power savings factor
------------------------- -
V
EXTERNAL COMPONENTS
V
–
0.1µF
DDINTNOM
DDINTRED
ZHCS1000
10µH
CCLKRED
CCLKNOM
⎞
⎠
2
FDS9431A
⎛
⎝
------------ -
T
T
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
NOM
RED
Figure 4
⎞
⎠
Rev. A | Page 13 of 60 | May 2006
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CLOCK SIGNALS
The ADSP-BF561 can be clocked by an external crystal, a sine
wave input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor CLKIN pin. When an external clock
is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF561 includes an on-chip
oscillator circuit, an external crystal may be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant, fun-
damental frequency, microprocessor-grade crystal should be
used.
As shown in
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user-programmable 0.5 to 64 multiplica-
tion factor. The default multiplier is 10 , but it can be modified
by a software instruction sequence. On the fly frequency
changes can be effected by simply writing to the PLL_DIV
register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
CLKIN
REQUI RES PLL SEQ UENCING
Figure
“FI NE” ADJUSTMENT
Figure 6. Frequency Modification Methods
0.5 to 64
Figure 5. External Crystal Connections
PLL
CLKIN
6, the core clock (CCLK) and system
XTAL
SCLK
SCLK
VCO
133 MHz
CCLK
Figure
CLKOUT
“CO ARSE” ADJUSTMENT
÷ 1 to 15
÷ 1, 2, 4, 8
ADSP-BF561
ON-THE-FLY
5.
CCLK
SCLK