ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 3

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ADSP-BF561_06

Manufacturer Part Number
ADSP-BF561_06
Description
Blackfin Embedded Symmetric Multiprocessor
Manufacturer
AD [Analog Devices]
Datasheet
REVISION HISTORY
5/06—Changes from Rev. 0 to Rev. A
Minor format and wording changes throughout the docunment.
Changed voltage range in
Changed PLL multiplier range in
Changed figure
Changed title of
Moved section
Replaced section
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Added section
Added section
Reformated table
Changed
Changed C
Changed
Added
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Changed Core Clock Requirements
Added
Changed figure
Changed
Changed
Changed figures in
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Rewrote/Changed values in
Rewrote section
Changed title of
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Reordered
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1/05—Initial version
Maximum Duty Cycle for Input Transient Voltage. 21
Package Information....................................... 21
Maximum SCLK Conditions............................. 22
Table 37....................................................... 48
Figure 47
Figure 45
Table 39....................................................... 53
Recommended Operating Conditions .............. 20
Absolute Maximum Ratings........................... 21
SDRAM Interface Timing ............................. 26
Parallel Peripheral Interface Timing................. 28
Ordering Guide .......................................... 58
Table 36 .................................................. 46
Table 38 .................................................. 51
IN
in
EZ-KIT Lite Evaluation Board ................. 16
Related Documents............................... 16
Timers .............................................. 10
Blackfin Processor Core..........................5
Clock and Reset Timing ....................... 23
Serial Ports ........................................ 32
Frequency Modification Methods ........... 13
Electrical Characteristics....................... 20
Table 2 ..............................................8
Test Conditions ................................. 43
Figure 37
Parallel Peripheral Interface ................. 11
and
and
Pin Descriptions............................... 17
Surface Mount Design ...................... 57
Parallel Peripheral Interface Timing.... 28
Figure 48 ................................... 50
Figure 46 ................................... 50
Features.................................1
through
Power Dissipation ............... 42
Peripherals ...................1
Figure 44.................. 44
............................. 22
Rev. A | Page 3 of 60 | May 2006
ADSP-BF561

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