ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 32

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ADSP-BF561_06

Manufacturer Part Number
ADSP-BF561_06
Description
Blackfin Embedded Symmetric Multiprocessor
Manufacturer
AD [Analog Devices]
Datasheet
ADSP-BF561
RSCLK
RFS
DR
TSCLK
DT
DT
DT
TFS
TFS ("LATE", EXT.)
TFS ("LATE", INT.)
DATA RECEIVE—INTERNAL CLOCK
TSCLK (EXT)
TSCLK (INT)
DATA TRANSMIT—INTERNAL CLOCK
t
HOFSE
t
HOFSI
t
HDTI
DRIVE
EDGE
DRIVE
EDGE
t
DFSE
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DDTI
DFSI
DRIVE
EDGE
DRIVE
EDGE
t
t
SCLKIW
SCLKIW
t
t
SFSI
t
SDRI
SFSI
t
DTENI
t
DTENE
SAMPLE
SAMPLE
EDGE
EDGE
Rev. A | Page 32 of 60 | May 2006
t
t
HDRI
t
HFSI
HFSI
Figure 17. Serial Ports
TSCLK / RSCLK
TSCLK / RSCLK
RFS
TSCLK
DT
RSCLK
DR
TFS
DATA RECEIVE—EXTERNAL CLOCK
DATA TRANSMIT—EXTERNAL CLOCK
t
t
HOFSE
HOFSE
t
HDTE
DRIVE
DRIVE
EDGE
EDGE
DRIVE
DRIVE
EDGE
EDGE
t
t
DFSE
DFSE
t
DDTE
t
t
SCLKEW
SCLKEW
t
DDTTI
t
t
t
SFSE
SDRE
SFSE
t
DDTTE
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HDRE
HFSE
HFSE

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