ADSP-TS201SABP-6X AD [Analog Devices], ADSP-TS201SABP-6X Datasheet
ADSP-TS201SABP-6X
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ADSP-TS201SABP-6X Summary of contents
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... Y REGISTER 128 128 FILE FILE DAB DAB 32x32 32x32 COMPUTATIONAL BLOCKS Figure 1. Functional block diagram One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 Fax:781/326-8703 TigerSHARC Embedded Processor ADSP-TS201S Table 1) JTAG PORT SOC BUS 6 JTAG EXTERNAL PORT HOST 64 MULTI PROC ...
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... Provides unused pin termination data in Descriptions (page 13). • Changes pins R2 and mm) BGA_ED Pin Assignments (page Pin Function Descriptions ........................................ 12 Strap Pin Function Descriptions ................................ 19 ADSP-TS201S—Specifications ................................... 21 Recommended Operating Conditions ...................... 21 Electrical Characteristics ....................................... 21 Absolute Maximum Ratings ................................... 22 ESD Sensitivity ................................................... 22 Timing Specifications ........................................... 23 General AC Timing .......................................... 23 Link Port Low-Voltage, Differential-Signal (LVDS) Output Drive Currents ...
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... ADSP- Figure 2. ADSP-TS201S Single-Processor System With External SDRAM The TigerSHARC DSP uses a Static Superscalar This architecture is superscalar in that the ADSP-TS201S pro- cessor’s core can execute simultaneously from one to four 32-bit instructions encoded in a Very Large Instruction Word (VLIW) instruction line using the DSP’ ...
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... FIR filters. DUAL INTEGER ALU (IALU) The ADSP-TS201S processor has two IALUs that provide pow- erful address generation capabilities and perform many general- purpose integer operations. The IALUs are referred and K in assembly syntax and have the following features: • ...
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... The ADSP-TS201S processor internal memory has 24M bits of on-chip DRAM memory, divided into six blocks of 4M bits (128K words × 32 bits). Each block—M0, M2, M4, M6, M8, and M10— ...
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... Host Interface The ADSP-TS201S processor provides an easy and configurable interface between its external bus and host processors through the external port. To accommodate a variety of host processors, Rev. PrH | Page December 2003 ...
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... HBG and relinquishes the exter- nal bus. The host can directly read or write the internal memory of the ADSP-TS201S processor, and it can access most of the DSP reg- isters, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands. ...
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... SDA10 CONTROLIMP1–0 CONTROL DS2–0 JTAG Figure 4. ADSP-TS201S Shared Memory Multiprocessing System LINK PORTS (LVDS) The DSP’s four full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using Low- Voltage, Differential-Signal (LVDS) technology. With the abil- ity to operate at a double data rate— ...
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... After reset, the ADSP-TS201S processor has four boot options for beginning operation: • Boot from EPROM. • Boot by an external master (host or another ADSP-TS201S processor). • Boot by link port. • No boot—Start running from memory address selected with one of the IRQ3–0 interrupt signals. See Using the ‘ ...
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... V DD_IO Figure 7. SCLK_V Filtering Scheme REF DEVELOPMENT TOOLS The ADSP-TS201S processor is supported with a complete set † of CROSSCORE software and hardware development tools, including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS201S processor ...
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... File (LDF), allowing the developer to move between the graphi- cal and textual environments. Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-TS201S processor to monitor and con- trol the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modifi- cation of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’ ...
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... For details, see Reset and Booting on page au Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN. au Power On Reset for internal DRAM. Connect to RST_OUT. on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website Ratio ...
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... RD. RD changes concurrently with ADDR pins. epu Write Low. WRL is asserted in two cases: When the ADSP-TS201S processor writes to an even address word of external memory or to another external bus agent; and when the ADSP-TS201S processor writes to a 32-bit zone (host, memory or DSP programmed to 32-bit bus). An external master (host or DSP) asserts WRL for writing to a DSP’ ...
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... ADSP-TS201S Table 6. Pin Definitions—External Port Arbitration Signal Type BR7–0 I/O ID2–0 I (pd BOFF I BUSLOCK O/T (pu_0) HBR I HBG I/O/T (pu_0) CPA I/O/OD (pu_od_0) DPA I/O/OD (pu_od_0 input asynchronous output open drain output Three-State power supply ground internal pulldown internal pullup pd_0 = internal pulldown DSP ID=0; pu_0 = internal pullup DSP ID=0 ...
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... HDQM is valid on SDRAM transactions when CAS is asserted, and inactive on read transactions. On write transactions, HDQM is active when accessing an even address in word accesses or when memory is configured for a 32-bit bus to disable the write of the high word. Rev. PrH | Page December 2003 ADSP-TS201S Electrical Characteristics on page 22. ; epu = External pull-up approximately Figure 3 on page 6) ...
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... ADSP-TS201S Table 8. Pin Definitions—External Port SDRAM Controller (Continued) Signal Type SDA10 O/T (pu_0) SDCKE I/O/T (pu_m/ pd_m) SDWE I/O/T (pu_0 input asynchronous output open drain output Three-State power supply ground internal pulldown internal pullup pd_0 = internal pulldown DSP ID=0; pu_0 = internal pullup DSP ID=0 ...
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... Not connected Always used. DD_IO 1 The L1BCMPO and L2BCMPO pins have different termination requirements on revision 0.x silicon, see the EE-179: ADSP-TS20xS TigerSHARC System Design Guidelines on the Analog Devices website (www.analog.com). Description FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin can be configured individually for input or for output. FLAG3– ...
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... ADSP-TS201S Table 12. Pin definitions—Impedance Control , Drive Strength Control, and Regulator Enable Signal Type CONTROLIMP0 I (pd) CONTROLIMP1 I (pu) DS2,0 I (pu) DS1 I (pd) ENEDREG I (pu input asynchronous output open drain output Three-State power supply ground internal pulldown internal pullup pd_0 = internal pulldown DSP ID=0; pu_0 = internal pullup DSP ID=0 ...
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... No Connect. Do not connect these pins to anything (not to any supply, signal, or each other). These pins are reserved and must be left unconnected. on revision 0.0 silicon, see the EE-179: ADSP-TS20xS TigerSHARC System Design Guidelines on the Analog Devices website logic inputs, a stronger external pullup or pulldown may be required to ensure default value depending on leakage and/or low level input current of the logic load ...
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... ADSP-TS201S Table 15. Pin Definitions—I/O Strap Pins (Continued) Signal Type (at Reset) SYS_REG_WE I (pd_0) TM1 I (pu) TM2 I (pu) TM3 I (pu input asynchronous output open drain output Three-State power supply ground internal pulldown internal pullup pd_0 = internal pulldown DSP ID=0; pu_0 = internal pullup DSP ID=0 ...
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... Differs for 600 MHz and 500 MHz parts. For more information, see 2 Applies to input and bidirectional pins. 3 For details on internal and external power calculation issues, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices website. 4 For ENEDREG=1, the internal DRAM supply is used; there the clock driver voltage is > ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-TS201S features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. – ...
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... FLAG3–0 (input only) pins, all AC timing for the ADSP-TS201S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSP- TS201S processor has few calculated (formula-based) values. For information on AC timing, see ...
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... ADSP-TS201S Table 20. Power-Up Reset Timing Parameter Timing Requirements t RST_IN Deasserted After V RST_IN_PWR Static/Strap Pins Stable 1 t TRST Asserted During Power-Up Reset TRST_IN_PWR Switching Characteristic t RST_OUT Deasserted After RST_IN Deasserted RST_OUT_PWR 1 Applies after (ENEDREG=0), and SCLK are stable and before RST_IN deasserted. ...
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... Rev. PrH | Page December 2003 ADSP-TS201S 4.0 1.0 1.15 2.0 SCLK 4.0 1.0 1.15 2.0 SCLK 4.0 1.0 1.15 2.0 SCLK 4.0 1.0 1.15 2.0 SCLK 4.0 1.0 1.15 2.0 SCLK 4.0 1.0 1.15 2.0 SCLK 4.0 1.0 1.15 2.0 SCLK 4.0 1.0 1.15 2.0 SCLK 3.6 2.0 1.15 2.0 SCLK 4.2 2.0 1.15 2.0 SCLK 4.0 1.0 1 ...
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... ADSP-TS201S Table 22. AC Signal Specifications (Continued) (all values in this table are in nanoseconds) Name Description 6 DS2–0 Static pins – must be constant 6 SCLKRAT2–0 Static pins – must be constant ENEDREG Static pins – must be connected to V 7,8 STRAP SYS Strap pins 9 JTAG SYS ...
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... 100 O_P O_N 100 O_N 100 O_P O_N Test Conditions (V O_P + V O_N ) 2 Rev. PrH | Page December 2003 ADSP-TS201S Min Max 1.58 0.92 150 450 = 0 V +5/- 40 +/- 5 1.13 1.38 Min Max 100 600 0.6 1.57 Units Units ...
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... ADSP-TS201S Link Port—Data Out Timing Table 25 with Figure 14, Figure 15, Figure Figure 18, and Figure 19 provide the data out timing for the LVDS link ports. Table 25. Link Port—Data Out Timing Parameter Outputs t Rising Edge (Figure REO t Falling Edge (Figure FEO t LxCLKOUT Period ...
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... LDOS LxDATO Figure 16. Link Ports—Data Output Setup and Hold 1 These parameters are valid for both clock edges LxCLKOUT LxDATO LxACKI LxBCMPO t LDOH 1 t LACKID t BCMPOV Figure 17. Link Ports—Transmission Start Rev. PrH | Page December 2003 ADSP-TS201S ...
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... ADSP-TS201S LxCLKOUT LxDATO LxACKI LxBCMPO LxCLKOUT LxDATO LxACKI FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD LAST EDGE IN A QUAD WORD t LACKIS t BCMPOH Figure 18. Link Ports—Transmission End and Stops t LACKIS Figure 19. Link Ports—Back to Back Transmission Rev ...
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... OD t BCMPIS Figure 20. Link Ports—Last Received Quad Word t FEI 1 These parameters are valid for both clock edges Rev. PrH | Page December 2003 ADSP-TS201S Max 1 CCLK 400 400 LCLKIP 1 LCLKIP FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD ...
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... Figure 30 show typical I–V characteristics for the output drivers of the ADSP-TS201S processor. The curves in these diagrams represent the current drive capability of the out- put drivers as a function of output voltage over the range of drive strengths. For complete output driver characteristics, refer to the DSP’ ...
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... DD_IO V = 2.625V, –40°C DD_IO I OH 2.0 2.4 2.8 Rev. PrH | Page December 2003 ADSP-TS201S 26. These include output disable time, output INPUT OR 1.25V Figure 31. Voltage reference levels for AC measurements (except out- put enable/disable) . This decay time can be approximated by the fol ...
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... ADSP-TS201S Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. The time for the voltage on the bus to ramp dependent on the capacitive load and the drive current, I ...
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... Strength 0.0393x + 2.7653 Strength 0.0373x + 2.6515 Strength 0.0379x + 2.1206 Strength 0.0399x + 1.9080 FALL TIME y = 0.0906x + 0.4597 100 = 2.5 V) vs. DD_IO Rev. PrH | Page December 2003 ADSP-TS201S STRENGTH 2.5V) DD_IO RISE TIME y = 0.0907x + 1.0071 0.09x + 0.3134 ...
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... For a more detailed pin summary diagram, see the EE-179: ADSP-TS201S System Design Guidelines on the Analog Devices website (www.analog.com) Table × BGA_ED package. = –40°C to CASE Table 27. Thermal Characteristics for 25 mm × Package Parameter ...
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... DD V G19 G20 V DD_IO DD_IO ADDR13 G21 ADDR7 ADDR12 G22 ADDR6 ADDR9 G23 ADDR5 ADDR8 G24 ADDR4 Rev. PrH | Page December 2003 ADSP-TS201S Pin# Signal Name D1 DATA55 D2 DATA56 D3 DATA54 DATA48 D6 DATA46 D7 DATA40 D8 DATA36 D9 DATA32 D10 DATA28 ...
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... ADSP-TS201S Table 28. 576-Ball (25 mm × 25 mm) BGA_ED Pin Assignments (Continued) Pin# Signal Name Pin# J1 RAS K1 J2 CAS REF J10 V K10 SS J11 V K11 SS J12 V K12 SS J13 V K13 SS J14 ...
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... AA24 L1DATO0_P AB24 1 On revision 1.x silicon, the R2 and R3 pins are NC. On revision 0.x silicon, the R2 pin is SCLK, and the R3 pin is SCLK_V on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website (www.analog.com). Signal Name Pin# Signal Name MSSD2 ...
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... THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10mm OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. 4. CENTER DIMENSIONS ARE N OMINAL. 5. THIS PACKAGE C ONFORMS WITH TH E JEDEC MS-034 SPECIFICATION. ORDERING GUIDE 1,2,3,4 Part Number ADSP-TS201SABP-6X ADSP-TS201SABP indicates 1.0/2.5 V supplies indicates –40°C to 85°C temperature indicated thermally enhanced Ball Grid Array (BGA_ED) package ...