ADSP-TS201SABP-6X AD [Analog Devices], ADSP-TS201SABP-6X Datasheet - Page 12

• Manufacturer Part Number: ADSP-TS201SABP-6X
• Description: TigerSHARC-R Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS201S
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS201S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. Use the
AC specification for asynchronous signals when the system
design requires predictable, cycle-by-cycle behavior for these
signals.
Table 3. Pin Definitions—Clocks and Reset
1
Table 4. SCLK Ratio
Signal
SCLKRAT2–0
SCLK
RST_IN
RST_OUT
POR_IN
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5 k ; pu = internal pullup 5 k ; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP
ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP
bus master; pu_ad = internal pullup 40 k ; For more pulldown and pullup information, see
Term (for termination) column symbols: epd = External pull-down approximately 5 k to V
to V
SCLKRAT2–0
000 (default)
001
010
011
100
101
110
111
For more information on SCLK and SCLK_V
(www.analog.com).
DD_IO
, nc = Not connected; au = Always used.
Type
I (pd)
I
I/A
O
I/A
1
REF
Ratio
4
5
6
7
8
10
12
Reserved
on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website
au
au
au
au
au
Term
Rev. PrH | Page 12 of 40 | December 2003
Description
Core Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is user-
programmable using the SCLKRATx pins to the values shown in
must have a constant value while the DSP is powered. The core clock rate (CCLK) is
the instruction cycle rate.
System Clock Input. The DSP’s system input clock for cluster bus.The core clock rate
is user-programmable using the SCLKRATx pins.
Domains on page 9.
Reset. Sets the DSP to a known state and causes program to be in idle state. RST_IN
must be asserted a specified time according to the type of reset operation. For details,
see
Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN.
Power On Reset for internal DRAM. Connect to RST_OUT.
Reset and Booting on page
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these
pins to get to their internal pullup or pulldown state. Some pins
have an internal pullup or pulldown resistor (±30% tolerance)
that maintains a known value during transitions between differ-
ent drivers.
9,
Table 19 on page
Preliminary Technical Data
Electrical Characteristics on page
SS
; epu = External pull-up approximately 5 k
For more information, see Clock
24, and
Figure 9 on page
Table
4. These pins
22.
25.