ADSP-TS201SABP-6X AD [Analog Devices], ADSP-TS201SABP-6X Datasheet - Page 28

• Manufacturer Part Number: ADSP-TS201SABP-6X
• Description: TigerSHARC-R Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS201S
Link Port—Data Out Timing
Table 25
Figure
LVDS link ports.
Table 25. Link Port—Data Out Timing
1
2
3
4
5
Parameter
Outputs
t
t
t
t
t
t
t
t
t
t
t
Inputs
t
t
Timing is relative to the 0 differential voltage (V
LCR (Link port Clock Ratio) = 1, 1.5, 2 or 4. t
The 2.5 value for t
t
TSW is a short-word transmission period. For a 4-Bit Link it is 2×LCR×t
REO
FEO
LCLKOP
LCLKOH
LCLKOL
COJT
LDOS
LDOH
LACKID
BCMPOV
BCMPOH
LACKIS
LACKIH
LDOS
Figure 14. Link Ports—Differential Output Signals Transition Time
and t
–
18, and
+
|
|
V OD
V OD
with
LDOH
V OD = 0V
|
|
values include LCLKOUT jitter.
MIN
MIN
Figure
Figure 19
LDOS
R L
V O_P
V O_N
applies for LCLKOUT 100 MHz.
Rising Edge
Falling Edge
LxCLKOUT Period
LxCLKOUT High
LxCLKOUT Low
LxCLKOUT Jitter
LxDATO Output Setup, LCR = 1 and LCR = 1.5
LxDATO Output Setup, LCR = 2 and LCR = 4
LxDATO Output Hold, LCR = 1 and LCR = 1.5
LxDATO Output Hold, LCR = 2 and LCR = 4
Delay from LxACKI rising edge to first transmission clock
edge
LxBCMPO Valid
LxBCMPO Hold
LxACKI low setup to guarantee that the transmitter stops
transmitting
LxACKI high setup to guarantee that the transmitter
continues its transmission without any interruption
(Figure
LxACKI high hold time
14,
Figure
provide the data out timing for the
C L
(Figure
19).
t
REO
15,
(Figure
(Figure
(Figure
17)
C L_N
C L_P
Figure
(Figure
CCLK
(Figure
(Figure 15
(Figure
(Figure
(Figure
OD
is the core period. Note that LCLK can be a maximum of 500 MHz (for example, if LCR=1 then CCLK must be 500 MHz.).
14)
14)
18).
= 0)
t
FEO
16,
(Figure
15)
18).
17)
15)
15)
Figure
Rev. PrH | Page 28 of 40 | December 2003
C L_P = 5pF
18).
R L = 100
C L = 0.1pF
C L_N = 5pF
17,
CCLK
and for a 1-Bit Link is 8×LCR×t
(Figure
(Figure
(Figure
(Figure
16)
16)
16) 0.25×LCR×t
16) smaller of 2.5
Min
greater of 2.0 or
0.9×LCR×t
0.4×t
0.4×t
0.25×LCR×t
smaller of 2.5
0.25×LCR×t
0.25×LCR×t
3×TSW - 0.5
14×LCR×t
0.5
1
LxCLKOUT
LCLKOP
LCLKOP
V OD = 0V
CCLK
1
1
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
1,,5
3
3
1,2
Figure 15. Link Ports—Output Clock
1,2
Preliminary Technical Data
or
or
ns
– 0.15
– 0.3
– 0.15
– 0.3
t
COJT
1,2,4
1,2,4
1,2,4
1,2,4
t
LCLKOH
t
Max
200
200
1.1×LCR×t
0.6×t
0.6×t
–/+70
14×LCR×t
2×LCR×t
LCLKOP
LCLKOP
LCLKOP
t
LCLKOL
CCLK
CCLK
1
1
CCLK
1,2
1,2
1,2
Units
ps
ps
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns