ADSP-TS201SABP-6X AD [Analog Devices], ADSP-TS201SABP-6X Datasheet - Page 23

• Manufacturer Part Number: ADSP-TS201SABP-6X
• Description: TigerSHARC-R Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
TIMING SPECIFICATIONS
With the exception of DMAR3–0, IRQ3–0, TMR0E, and
FLAG3–0 (input only) pins, all AC timing for the ADSP-TS201S
processor is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSP-
TS201S processor has few calculated (formula-based) values.
For information on AC timing, see
page
Port Low-Voltage, Differential-Signal (LVDS) Electrical Char-
acteristics and Timing on page
Table 17. AC Asynchronous Signal Specifications (all values in this table are in nanoseconds)
1
2
3
Table 18. Reference Clocks
1
2
3
4
Table 19. Power-Up Reset Timing
1
Name
IRQ3–0
DMAR3–0
FLAG3–0
TMR0E
Signal
CCLK
SCLK
TCK
Parameter
Timing Requirements
t
t
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.
For output specifications on FLAG3–0 pins, see
This pin is a strap option. During reset, an internal resistor pulls the pin low.
CCLK is the internal DSP clock or instruction cycle time. The period of this clock is equal to the System Clock (SCLK) period divided by the System Clock Ratio (SCLKRAT2–0).
Actual input jitter should be combined with ac specifications for accurate timing analysis.
For more information, see
For more information, see Clock Domains on page 9.
Applies only when the internal DRAM regulator is disabled (ENEDREG=0)
For information on available part numbers for different internal DSP clock rates, see the
VDD_DRAM
VDD_DRAM_RAMP
24. For information on Link port transfer timing, see
2,3,4
1
3
1
1
2
1
V
DD_DRAM
V
V
DD_IO
DD_A
V
V
V
DD
Type Description
–
I
I
DD_DRAM
DD_DRAM
Table 3 on page
Stable After V
Supply Rise Time
Core Clock
System Clock
Test Clock (JTAG)
Description
Interrupt Request
DMA Request
FLAG3–0 Input
Timer 0 Expired
28.
General AC Timing on
13.
DD
Table
t
, V
VDD_DRAM
t
DD_A
VDD_DRAM_RAMP
22.
Speed
Grade
(MHz)
600
500
All
All
, V
Rev. PrH | Page 23 of 40 | December 2003
DD_IO
Stable
Clock
Cycle
Min (ns)
1.67
2.0
Greater of 8 or CCLK×4
Greater of 30 or CCLK×4
Figure 8. Power-Up Timing
Link
Pulsewidth Low (min)
2 × t
2 × t
2×t
4×t
Ordering Guide on page
General AC Timing
Timing is measured on signals when they cross the 1.25 V level
as described in
onds) are measured between the point that the first signal
reaches 1.25 V and the point that the second signal reaches
1.25 V.
The general AC timing data appears in
The AC asynchronous timing data for the IRQ3–0, DMAR3–0,
FLAG3–0, and TMR0E pins appears in
SCLK
SCLK
SCLK
SCLK
ns
ns
ns
ns
Clock
Cycle
Max (ns)
12.5
12.5
50
–
Figure 11 on page
42.
Clock
High
Min (ns)
–
–
12
{40% to 60% Duty Cycle} 100
Min
0
Pulsewidth High (min)
2 × t
2 × t
2×t
–
27. All delays (in nanosec-
SCLK
SCLK
SCLK
Clock
Low
Min (ns)
–
–
12
ns
ns
ns
Table 18
Table
Max
0.2
ADSP-TS201S
17.
and
Input
Jitter
Tolerance
(ps)
–
–
–
Table
Units
ms
ms
22.