ADSP-TS201SABP-6X AD [Analog Devices], ADSP-TS201SABP-6X Datasheet - Page 34

• Manufacturer Part Number: ADSP-TS201SABP-6X
• Description: TigerSHARC-R Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS201S
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by V is
dependent on the capacitive load, C
This ramp time can be approximated by the following equation:
The output enable time t
t
t
switches to when the output voltage ramps V from the mea-
sured three-stated output level. t
C
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF.
through
itance.
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see
page
linear outside the ranges shown.
MEASURED_ENA
MEASURED_ENA
L
, drive current I
Figure 34. Typical Output Rise and Fall Time (10%–90%, V
Load Capacitance at Strength 0
34.) The graphs of
Figure 42
Figure 33. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
25
20
15
10
Figure 41
5
0
0
and t
is the interval from when the reference signal
y = 0.2015x + 3.8869
10
OUTPUT
PIN
graphically shows how output valid varies with
TO
RISE TIME
D
RAMP
show how output rise time varies with capac-
20
, and with V equal to 0.4 V.
t
RAMP
Figure
30
as shown in
Figure 34
LOAD CAPACITANCE – pF
ENA
40
(V
is the difference between
33). The delay and hold specifica-
=
STRENGTH 0
30pF
DD_IO
50
RAMP
C
through
L
Output Disable Time on
= 2.5V)
L
Figure
50
60
, and the drive current, I
V
is calculated with test load
70
I
y = 0.174x + 2.6931
D
Figure 42
32. The time
1.25V
FALL TIME
80
Figure 34
Rev. PrH | Page 34 of 40 | December 2003
90
DD_IO
may not be
100
= 2.5 V) vs.
D
.
Figure 35. Typical Output Rise and Fall Time (10%–90%, V
Load Capacitance at Strength 1
Figure 36. Typical Output Rise and Fall Time (10%–90%, V
Load Capacitance at Strength 2
Figure 37. Typical Output Rise and Fall Time (10%–90%, V
Load Capacitance at Strength 3
25
20
15
10
25
20
15
10
25
20
15
10
5
0
5
0
5
0
0
0
0
y = 0.1082x + 1.3123
y = 0.1349x + 1.9955
y = 0.1304x + 0.8427
10
10
10
RISE TIME
RISE TIME
Preliminary Technical Data
RISE TIME
20
20
20
30
30
30
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
40
40
40
(V
(V
(V
STRENGTH 2
STRENGTH 1
STRENGTH 3
DD _IO
DD_IO
DD_IO
50
50
50
= 2.5V)
= 2.5V)
= 2.5V)
60
60
60
70
70
70
y = 0.1144x + 0.7025
y = 0.1163x + 1.4058
y = 0.0912x + 1.2048
FALL TIME
80
80
80
FALL TIME
FALL TIME
90
90
90
DD_IO
DD_IO
DD_IO
100
100
100
= 2.5 V) vs.
= 2.5 V) vs.
= 2.5 V) vs.