MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 17

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Control Register, Interrupt Control Register, Recei-
ver Control Register, Transmitter Control Register,
Sync Word 1, and Sync Word 2. The Mode Control
Register must be programmed before other regis-
ters to assure proper operation of the SIO. The fol-
lowing registers are used to transfer data or
communicate status between the SIO and the CPU
or other bus master : Command Register, Status
Register 0, Status Register 1, Data Register, and
the Vector Register.
The SIO provides four I/O lines in Synchronous
modes that may be used for modem control, for ex-
ternal interrupts, or as general purpose I/O. The Re-
quest To Send (RTS) and Data Terminal Ready
(DTR) pins are outputs that follow the inverted state
of their respective bits in the Transmit Control Re-
gister. The Data Carrier Detect (DCD) and Clear To
Send (CTS) pins are inputs that can be used as auto
enables to the receiver and transmitter, respective-
ly. If External/Status Interrupts are enabled, the
DCD and CTS pins will be monitored for a change
of status. If these inputs change for a period of time
greater than the minimum specified pulse width, an
interrupt will be generated.
In the following discussion, all interrupt modes are
assumed enabled.
SYNCHRONOUS TRANSMIT
Initialization. Byte-oriented transmitter programs
are usually initialized with the following parameters :
Figure 10 : Synchronous Formats.
odd-even or no parity, x1 clock mode, 8- or 16-bit
sync character(s), CRC polynomial, Transmit En-
ables, interrupt modes, and transmit character
length. If Parity is enabled, the transmitter will only
add a parity bit to a character that is loaded into the
transmit buffer ; it will not add a parity bit to the auto-
matically inserted sync character(s) or the CRC
characters.
One of two polynomials may be used with Synchro-
nous modes, CRC-16 (X
CRC (X
(SDLC mode not selected), the CRC generator and
checker are reset to all zeros. Both the receiver and
transmitter use the same polynomial.
After reset (hardware or software), or when the
transmitter is not enabled, the Transmit Data (TxD)
output pin is held High (marking). Under program
control, the Send Break bit in the Transmitter Control
Register can be set to a one, forcing the TxD output
pin to a Low level (spacing), even if the transmitter
is not enabled. The spacing condition will persist un-
til the Send Break bit is reset to a zero. A program-
med break is effective as soon as it is written into the
Transmit Control Register ; any characters in the
transmit buffer and transmit shift register are lost.
If the transmit buffer is empty when the Transmit En-
able bit is set to a one, the transmitter will start sen-
ding 8- or 16-bit sync characters. Continuous syncs
will be transmitted on the TxD output pin, as long as
no data is loaded into the transmit buffer. Note, if a
16
+ X
12
+ X
5
+ 1). For either polynomial
16
+ X
15
+ X
2
+1) or SDLC-
V000383
17/46