MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 6

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

DMA INTERFACE
The SIO is designed to interface to the 68000 family
DMA’s as a 68000 compatible device, using the cy-
cle steal mode. The SIO provides four outputs
(TxRDYA, RxRDYA, TxRDYB, RxRDYB) for re-
questing service from the DMA. The SIO issues are-
quest for service by pulsing the RDY pin low for three
clock (CLK) cycles (see figure 4). TxRDY (when en-
abled) will be active when the transmit buffer be-
comes empty. RxRDY (when enabled) will be active
when a character is available in the receive buffer.
If Receive Interrupt On First Character Only is en-
abled during a DMA operation and a special receive
condition is detected, the RxRDY pin will not be-
come active. Instead, a special receive condition in-
terrupt will be generated by the channel.
RESET
There are two ways of resetting the SIO : an indivi-
dual, programmable channel reset and an external
hardware reset.
The individual channel reset is generated by writing
”18H” to the Command Register for the channel se-
lected. All outputs associated with the channel are
reset high, TxC and RxC are inputs, SYNC is an out-
put, and TxD is forced marking. All R/W registers for
the channel are reset to ”00H”, except the vector re-
gister and the data register, which are not affected.
Read only status register 1 is reset to ”01H” (All Sent
set). Break/Abort, Interrupt Pending, and Rx Char-
acter Available bits in read only status register 0 are
reset ; Underrun/EOM, Hunt/Sync, and Tx Buffer
Empty are set ; CTS and DCD bits are set to the in-
verted state of their respective input pins. Any inter-
rupts pending for the channel are reset (any pending
interrupts in the other channel will not be affected).
An external hardware reset occurs when the RESET
pin is driven low for at least one clock (CLK) cycle.
Both channels are reset as listed above, and the
vector register is reset to ”0FH”.
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ARCHITECTURE
The MK68564 SIO contains two independent, full-
duplex channels. Each channel contains a transmit-
ter, receiver, modem control logic, interrupt control
logic, a baud rate generator, ten Read/Write regis-
ters, and two read only status registers. Each chan-
nel can communicate with the bus master using pol-
ling, interrupts, DMA, or any combination of these
three techniques. Each channel also has the ability
to connect the transmitter output into the receiver wi-
thout disturbing any external hardware.
Register Set. The register set is the heart of each
channel. A channel is configured for different
communication protocols and interface options by
programming the registers. Table 1 lists all the re-
gisters available in the SIO and their addresses.
Data Register. The Data Register is composed of
two separate registers : a write only register, which
is the Transmit Buffer, and a read only register,
which is the Receive Buffer. The Receive Buffer is
also the top register of a three register stack called
the receive data FIFO.
Vector Register. The Vector Register is different
from the other 24 registers, because it may be ac-
cessed through either Channel A or Channel B du-
ring a R/W cycle. During an Interrupt Acknowledge
cycle, the contents of the Vector Register are pas-
sed to the CPU to be used as a pointer to an interrupt
service routine. If the Status Affects Vector bit is Low
in the Interrupt Control Register, any data written to
the Vector Register will be returned unmodified du-
ring a Read Cycle or an IACK cycle. If the Status Af-
fects Vector bit is High, the lower three bits of the
vectorreturned during a Read or IACK cycle are mo-
dified to reflect the highest priority interrupt pending
in the SIO at that time. The upper five bits written to
the Vector Register are unaffected. After a hardware
reset only, this register contains a ”0FH” value,
which is the MK68000’s uninitialized interrupt vector
assignment.