MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 33

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

CRC at the end of a message in Synchronous
modes. When a transmit underrun condition occurs
and this bit is low. CRC will be appended to the end
of the transmission, and this bit will be set. Only the
0-to-1 transition of this bit causes an External/Status
interrupt, when enabled. This bit is not used in Asyn-
chronous modes.
D5 : Clear To Send (CTS)
This bit indicates the inverted state of the CTS input
pin at the time of the last change of any of the five
External/Status bits. Any transition of the CTS input
causes the CTS bit to be latched and generates an
External/Status interrupt request, if enabled. To
read the current state of the CTS pin, this bit must
be read immediately following a Reset External/Sta-
tus Interrupts command (command 2).
D4 : Hunt/Sync
In Asynchronous modes, this bit indicates the inver-
ted state of the SYNC input pin at the time of the last
change of any of the five External/Status bits. Any
transition of the SYNC input causes the Hunt/Sync
bit to be latched and generates an External/Status
interrupt request, if enabled. To read the current
state of the SYNC pin, this bit must be read imme-
diately following a Reset External/Status Interrupt
command (command 2).
In External sync mode, the SYNC pin is used by ex-
ternal logic to signal character synchronization is a-
chieved, the SYNC pin is driven Low on the second
rising edge of the Receive Clock (RxC) on which the
last bit of the sync character was received. Once the
SYNC pin is Low, it should be held Low until the end
of the message and the driven back High. Both
transitions on the SYNC pin cause External/Status
interrupt requests, if enabled. The inverted state of
the SYNC pin is indicated by this bit.
In Monosync, Bisync, and SDLC modes, this bit in-
dicates when the receiver is in the Hunt mode. This
bit is set to a one following a hardware ir channel re-
set, after the Enter Hunt Mode bit is written High,
when the receiver is disabled, or when an Abort se-
quence (SDLC mode) is detected. This bit will re-
main in this state until character synchronization is
achieved. External/Status interrupt requests will be
generated on both transitions of the Hunt/Sync bit.
D3 : Data Carrier Detect (DCD)
This bit indicates the inverted state of the DCD input
pin at the time of the last change of any of the five
External/Status bits. Any transition of the DCD input
causes the DCD bit to be latched and generates an
External/Status interrupt request, if ena-bled. To
read the current state of the DCD pin, this bit must
be read immediately following a Reset External/Sta-
tus Interrupts command (command 2).
D2 : Transmit Buffer Empty
This bit is set to a one, when the transmit buffer be-
comes empty, and when the last CRC bit is trans-
mitted in Synchronous or SDLC modes. This bit is
reset when the transmit buffer is loaded or while the
CRC character is being sent in Synchronous or
SDLC modes. This bit is set to a one following a
hardware or channel reset.
D1 : Interrupt Pending
Any interrupt condition, pending in the interrupt
control logic for this channel, will set this bit to a one.
This bit is reset to zero by a hardware channel reset,
or when all the interrupt conditions are cleared.
D0 : Receive Character Available
This bit is set to a one when a character becomes
available in the receive data FIFO. This bit is reset
to zero when the receive data FIFO (receive buffer)
is read, or by a hardware or channel reset.
STATUS REGISTER 1 (STAT 1)
READ ONLY
This register contains the Special Receive Condition
status bits and the Residue codes for the I-field in the
SDLC receive mode. The All Sent bit is set High, and
all other bits are reset to a Low by a channel or hard-
ware reset.
D7 : End Of Frame (SDLC)
This bit is used only in SDLC mode. When set to a
one, this bit indicates that a valid closing flag has
been received and that the CRC/Framing Error bit
and Residue codes are valid. If receiver interrupts
are enabled, a Special Receive Condition interrupt
will also be generated. This bit can be reset by is-
suing an Error Reset command (command 6). This
bit is also updated by the first character of the follo-
wing frame. This bit is a zero in all modes except for
E ND OF
FRAME
D7
FRAME
ERROR
CRC/
D6
OVER-
RUN
D5
ERR
RX
PARITY
ERROR
D 4
RESIDUE
CODE 2
D 3
RESIDUE
CODE 1
D2
RESIDUE
CODE 0
D 1
33/46
SE NT
D 0
ALL