KSZ8842-16MBL-EVAL MICREL [Micrel Semiconductor], KSZ8842-16MBL-EVAL Datasheet - Page 38

• Manufacturer Part Number: KSZ8842-16MBL-EVAL
• Description: 2-Port Ethernet Switch with Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge of
ADSN to latch the incoming signals A [15:1], AEN, BE3N, BE2N, BE1N, and BE0N.
Note: Whether the transfer is synchronous or asynchronous, if the local device decoder is used, LDEVN will be asserted
to indicate that the KSZ8842M is successfully targeted. Basically, signal LDEVN is a combinatorial decode of AEN and
A[15:4].
Asynchronous Interface
For asynchronous transfers, the asynchronous dedicated signals RDN (for read) or WRN (for write) toggle, but the
synchronous dedicated signals BCLK, CYCLEN, SWR, and RDYRTNN are de-asserted and stay at the same logic level
throughout the entire asynchronous transfer.
There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU,
however, provides flexible asynchronous interfacing to communicate with various applications and architectures. Three
major ways of interfacing with the system (host) are.
Interfacing with the system/host relying on local device decoding and having stable address throughout the whole transfer:
Micrel, Inc.
October 2007
Signal
CYCLEN
SWR
SRDYN
RDYRTNN
BCLK
Asynchronous Transfer Signals
RDN
WRN
ARDY
Note 1: I = Input. O = Output. I/O = Bi-directional.
1. The typical example for this application is ISA-like bus interface using latched address signals as shown in the
2. Interfacing with the system/host relying on local device decoding but not having stable address throughout the
3. Interfacing with the system/host relying on central decoding (KSZ8842-32 mode only).
Figure 17. No additional address latch is required, therefore ADSN should be connected Low. The BIU decodes
A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8842M switch is the intended target. The
host utilizes the rising edge of RDN to latch read data and the BIU will use rising edge of WRN to latch write data.
entire transfer: the typical example for this application is EISA-like bus (non-burst) interface as shown in the
Figure 18. This type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched
A[15:4] and qualifies with AEN to determine if the KSZ8842M switch is the intended target. The data transfer is
the same as the first case.
The typical example for this application is for an embedded processor having a central decoder on the system
board or within the processor. Connecting the chip select (CS) from system/host to DATACSN bypasses the local
device decoder. When the DATACSN is asserted, it only allows access to the Data Register in 32 bits and BE3N,
Type
I
I
O
I
I
I
I
O
(1)
Function
For VLBus-like access: used to sample SWR when asserted.
For burst access: used to connect to IOWC# bus signal to indicate burst write.
Write/Read
For VLBus-like access: used to indicate write (High) or read (Low) transfer.
For burst access: used to connect to IORC# bus signal to indicate burst read.
Synchronous Ready
For VLBus-like access: exactly the same signal definition of nSRDY in VLBus.
For burst access: insert wait state by the KSZ8842M whenever necessary
during the Data Register access.
Ready Return
For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the
cycle.
For burst access: exactly like EXRDY signal in EISA to insert wait states. Note
that the wait states are inserted by system logic (memory) not by KSZ8842M.
Bus Clock
Asynchronous Read
Asynchronous Write
Asynchronous Ready
This signal is asserted (low) to insert wait states.
Table 2. Bus Interface Unit Signal Grouping
38
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9