KSZ8842-16MBL-EVAL MICREL [Micrel Semiconductor], KSZ8842-16MBL-EVAL Datasheet - Page 47

• Manufacturer Part Number: KSZ8842-16MBL-EVAL
• Description: 2-Port Ethernet Switch with Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

802.1p based priority is enabled by bit 5 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port,
respectively.
The KSZ8842M provides the option to insert or remove the priority tagged frame's header at each individual egress port.
This header, consisting of the 2 bytes VLAN protocol ID (VPID) and the 2 bytes tag control information field (TCI), is also
referred to as the 802.1Q VLAN tag.
Tag insertion is enabled by bit 2 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port, respectively.
At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in
register sets P1VIDCR, P2VIDCR, and P3VIDCR for ports 1, 2 and the host port, respectively. The KSZ8842M does not
add tags to already tagged packets.
Tag removal is enabled by bit 1 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port, respectively. At
the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8842M will not modify untagged
packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p priority field re-mapping is a QoS feature that allows the KSZ8842M to set the “User Priority Ceiling” at any
ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress
port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority Ceiling” is enabled by bit 3
of registers P1CR2, P2CR2, and P3CR2 for ports 1, 2, and the host port, respectively.
DiffServ based Priority
DiffServ-based priority uses the ToS registers shown in the Priority Control Registers section. The ToS priority control
registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to determine packet
priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully decoded, the
resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine priority.
Rate Limiting Support
The KSZ8842M supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and on the
“transmit side” on a per port basis. For 10-base T, a rate setting above 10 Mbps means the rate is not limited. On the
receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control
Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up
Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or
Preamble byte, in addition to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8842M provides options to selectively choose frames from all types, multicast, broadcast,
and flooded unicast frames. The KSZ8842M counts the data rate from those selected type of frames. Packets are
dropped at the ingress port when the data rate exceeds the specified rate limit.
Micrel, Inc.
October 2007
Bytes
802.1q VLAN Tag
Preamble
7
Bits
1
DA
6
Tagged Packet Type
(8100 for Ethernet)
16
SA
6
Figure 14. 802.1p Priority Field Format
VPID
2
802.1p
TCI
2
3
47
1
length
2
VLAN ID
12
KSZ8842-16/32 MQL/MVL/MVLI/MBL
46-1500
Data
M9999-102207-1.9
FCS
4