KSZ8842-16MBL-EVAL MICREL [Micrel Semiconductor], KSZ8842-16MBL-EVAL Datasheet - Page 65

• Manufacturer Part Number: KSZ8842-16MBL-EVAL
• Description: 2-Port Ethernet Switch with Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Bank 16 Transmit Control Register (0x00): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bank 16 Transmit Status Register (0x02): TXSR
This register keeps the status of the last transmitted frame.
Bank 16 Receive Control Register (0x04): RXCR
This register holds control information programmed by the CPU to control the receive function.
Micrel, Inc.
Bit
15
14
13
12-4
3
2
1
0
Bit
15-6
5-0
Bit
15-11
10
9
8
7
October 2007
Default Value
-
0x0
0x0
-
0x0
0x0
0x0
0x0
Default Value
-
Default Value
-
0x0
0x0
-
0x0
0x000
R/W
RO
RW
RW
RO
RW
RW
RW
RW
R/W
RO
RO
R/W
RO
RW
RW
RO
RW
Description
Reserved
Reserved
Reserved
Reserved
TXFCE Transmit Flow Control Enable
When this bit is set, the QMU sends flow control pause frames from the host port if the
RX FIFO has reached its threshold.
Note: the SGCR3[5] in Bank 32 also needs to be enabled.
TXPE Transmit Padding Enable
When this bit is set, the KSZ8842M automatically adds a padding field to a packet
shorter than 64 bytes.
Note: Setting this bit requires enabling the ADD CRC feature to avoid CRC errors for
the transmit packet.
TXCE Transmit CRC Enable
When this bit is set, the KSZ8842M automatically adds a CRC checksum field to the
end of a transmit frame.
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state.
When reset, the transmit process is placed in the stopped state after the transmission
of the current frame is completed.
Description
Reserved
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame with this ID.
Description
Reserved
RXFCE Receive Flow Control Enable
When this bit is set, the KSZ8842M will acknowledge a PAUSE frame from the receive
interface; i.e., the outgoing packets are pending in the transmit buffer until the PAUSE
frame control timer expires. When this bit is cleared, flow control is not enabled.
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue.
When reset, all CRC error frames are discarded.
Reserved
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
65
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9