MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 146

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Communications Processor (CP)
CD10–CD0—Clock Divider
When dividing by an odd number, the counter ensures a 50% duty cycle by asserting the
terminal count once on a clock high and next on a clock low. The terminal count signals the
counter expiration and toggles the clock.
DIV4—SCC Clock Prescaler Divide by 4
The SCC clock prescaler bit selects a divide-by-1 (DIV4 = 0) or divide-by-4 (DIV4 = 1) pres-
caler for the clock divider input. The divide-by-4 option is useful in generating very slow baud
rates.
4.5.2.1 Asynchronous Baud Rate Generator Examples
The UART circuitry always uses a clock that is 16x the baud rate. The ratio of the 16x UART
clock to the system parallel clock must not exceed 1:2.5. For an internally supplied clock, an
integer divider value must be used; therefore, the divider must be 3 or greater. Thus, using
a clock divider value of 3 (programmed as 2 in the SCON) and a 16.67-MHz crystal gives a
UART clock rate of 5.56 MHz and a baud rate of 347 kbaud. Assuming again a 16.67-MHz
4-26
The clock divider bits and the prescaler determine the baud rate generator output clock
rate. CD10–CD0 are used to preset an 11-bit counter that is decremented at the prescaler
output rate. The counter is not otherwise accessible to the user. When the counter reach-
es zero, it is reloaded with the clock divider bits. Thus, a value of $7FF in CD10–CD0 pro-
duces the minimum clock rate (divide by 2048); a value of $000 produces the maximum
clock rate (divide by 1).
CLOCK
MAIN
TIN 1
PIN
RCS
BIT
Because of SCC clocking restrictions, the maximum baud rate
that may be used to clock an SCC is divide by 3.
INTERNAL
R CLOCK
EXTC
MUX
MUX
BIT
Figure 4-12. SCC Baud Rate Generator
RCLK
PIN
MC68302 USER’S MANUAL
PRESCALER
DIVIDE BY
1 OR 4
DIV 4
BIT
NOTE
TCS
BIT
CD10–CD0
COUNTER
INTERNAL
T CLOCK
1-2048
11-BIT
BITS
MUX
EXTERNAL
PIN
TCLK
PIN
MOTOROLA