MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 409

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

A CP reset in the command register (CR) may be required to continue operation with an
SCC that has underrun or overrun.
There are two special points worth noting about gating clocks:
Providing less than nine extra clocks harms nothing, but the last word of the frame will not
be received until the next frame begins. If you need to get this last word of data into the buffer
without waiting for the next frame, an ENTER HUNT MODE command may be given. This
command will clear out the residue bits, allowing a new synchronization to occur for the next
frame. The ENTER HUNT MODE command should be given between the 9th and 16th se-
rial clock, after the last bit of the frame has been clocked into the MC68302 and at least three
serial clocks before the next CD (sync). Serial clocks do not need to be running while this
command is executed.
If normal CD is used, as opposed to CD (sync), the CD pin should remain asserted for at
least six additional clocks after the last bit of the frame is clocked in. After CD is negated, an
additional three receive clocks should also be provided before the clocks are stopped. Ad-
ditional clocks after CD is negated force ones into the SCC, regardless of the state of the
RXD pin. When you want a new frame to be clocked into the MC68302, CD should be as-
serted one clock prior to the first bit of the new frame. (Note that when normal CD is used,
the frame length need not be a multiple of 16 bits).
MOTOROLA
1. When gating clocks to the transmitter, be aware that clocks are required to the trans-
2. If you cleared the L bit in the Tx BDs, then you can freely gate the clocks at any time
3. Data may be freely gated to the receiver when the CD (sync) signal is used. However,
mitter for the Tx BD to be polled and the transmit FIFO to be initially filled with data.
You cannot enable the transmitter and begin providing clocks 1 ms later and expect
the transmit data to go out on the first clock provided. Neither is there a set number of
clocks to count on since the number of clocks is dependent on the data rate, the RISC
loading, the system bus latency, and the exact time in relation to the RISC poll that the
Tx BD ready bit was set. Therefore, it is best to use CTS or CD (sync) to gate data out
of the chip while initially providing a number of transmit clocks.
(for instance between buffers) and pick up right where you left off. If each frame is an
individual entity and the timing of the frame to follow it is unknown, then the L bit should
be set, and after RTS is negated by the MC68302 and CTS is negated by your external
logic, you may disable clocking the transmitter. However, be sure to give the transmit-
ter more clocks (20 should be enough in most systems), before expecting the RTS pin
to go low again, signifying that data is ready to be transmitted. The CTS or CD (sync)
pins may once again be used to control the exact timing of the subsequent data trans-
mission.
remember that nine extra clocks will need to be provided after the frame (which must
be a multiple of 16 bits) to ensure that the receive data passes through the SCC to the
FIFO where it can be extracted by the SDMA and moved to memory.
MC68302 USER’S MANUAL
MC68302 Applications
D-59