MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 213

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

SYNF—Transmit SYN1–SYN2 or IDLE between Messages and Control the RTS Pin
ENC—Data Encoding Format
COMMON SCC MODE BITS—See 4.5.3 SCC Mode Register (SCM) for a description of the
DIAG1, DIAG0, ENR, ENT, MODE1, and MODE0 bits.
4.5.13.10 BISYNC Receive Buffer Descriptor (Rx BD)
The first word of the Rx BD contains control and status bits.
E—Empty
MOTOROLA
OFFSET + 0
OFFSET + 6
OFFSET +2
OFFSET +4
character recognition and stripping is desired to be performed in software. The bit should
be set (or reset) within the time taken to receive the following data byte. When this bit is
reset, the BCS calculations exclude the latest fully received data byte. When RBCS is set,
the BCS calculations continue normally.
• The CP reports information about the received data for each buffer using BD. The Rx
• Receiving a user-defined control character
• Detecting an error
• Detecting a full receive buffer
• Issuing the ENTER HUNT MODE command
0 = Disable receive BCS
1 = Enable receive BCS
0 = Send ones between messages; RTS is negated between messages. The BISYNC
1 = Send SYN1–SYN2 pairs between messages; RTS is always asserted.
0 = Non-return to zero (NRZ). A one is a high level; a zero is a low level.
1 = Non-return to zero inverted (NRZI). A one is represented by no change in the level;
BD is shown in Figure 4-32. The CP closes the current buffer, generates a maskable
interrupt, and starts to receive data into the next buffer after one of the following events:
0 = The data buffer associated with this BD has been filled with received data, or data
1 = The data buffer associated with this BD is empty. This bit signifies that the BD and
controller can transmit ones in both NRZ and NRZI encoded formats.
a zero is represented by a change in the level. The receiver decodes NRZI, but a
clock must be supplied. The transmitter encodes NRZI.
reception has been aborted due to an error condition. The M68000 core is free to
examine or write to any fields of this BD.
its associated buffer are available to the CP. After it sets this bit, the M68000 core
15
E
14
X
Figure 4-32. BISYNC Receive Buffer Descriptor
13
W
12
I
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
11
C
MC68302 USER’S MANUAL
10
B
—
9
DATA LENGTH
—
8
—
7
—
6
Communications Processor (CP)
—
5
DL
4
PR
3
CR
2
OV
1
4-93
CD
0