MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 153

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

For frame-oriented protocols (HDLC, BISYNC, DDCMP, V.110), a frame may reside in as
many buffers as are necessary (transmit or receive). Each buffer has a maximum length of
64K–1 bytes. The CP does not assume that all buffers of a single frame are currently linked
to the BD table, but does assume that the unlinked buffers will be provided by the processor
in time to be either transmitted or received. Failure to do so will result in a TXE error being
reported by the CP.
For example, assume the first six buffers of the transmit BD table have been transmitted and
await processing by the M68000 core (with all eight buffers used in the circular queue), and
a three-buffer frame awaits transmission. The first two buffers may be linked to the remain-
ing two entries in the table as long as the user links the final buffer into the first entry in the
BD table before the IMP attempts its transmission. If the final buffer is not linked in time to
the BD table by the time the CP attempts its transmission, the CP will report an underrun
error.
Buffers allocated to an SCC channel may be located in either internal or external memory.
Memory allocation occurs for each BD individually. If internal memory is selected, the CP
uses only the lower 11 address bits (A10–A0) as an offset to the internal dual-port RAM. Ac-
cesses to the internal memory by the CP are one clock cycle long and occur without arbitra-
tion. If external memory is selected, the pointers to the data buffers are used by the CP as
24 bits of address.
Extra caution should be used if function codes are included in the decoding of the external
buffer address (e.g., in the on-chip chip select logic). The function code of this SCC channel
must be set before external buffers can be accessed; it can then be changed only when the
user is sure that the CP is not currently accessing external buffers for that channel. There
are six separate function code registers located in the parameter RAM for the three SCC
channels: three for receive data buffers (RFCR) and three for transmit data buffers (TFCR).
The CP processes the transmit BDs in a straightforward fashion. Once the transmit side of
an SCC is enabled, it starts with the first BD in that SCC's transmit BD table, periodically
checking a bit to see if that BD is "ready". Once it is ready, it will process that BD, reading a
word at a time from its associated buffer, doing certain required protocol processing on the
data, and moving resultant data to the SCC transmit FIFO. When the first buffer has been
processed, the CP moves on to the next BD, again waiting for that BD's “ready” bit to be set.
Thus, the CP does no look-ahead BD processing, nor does it skip over BDs that are not
ready. When the CP sees the “wrap” bit set in a BD, it goes back to the beginning of the BD
MOTOROLA
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
15
The RFCR and TFCR function codes should never be initialized
to “111.”
HIGH-ORDER DATA BUFFER POINTER (only lower 8 bits used, upper 8 bits must be 0)
Figure 4-16. SCC Buffer Descriptor Format
MC68302 USER’S MANUAL
LOW-ORDER DATA BUFFER POINTER
STATUS AND CONTROL
NOTE
DATA LENGTH
Communications Processor (CP)
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