CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 23

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in
Table 5-2. Device Configuration NVL Register Map
The details for individual fields and their factory default settings are shown in
Table 5-3. Fields and Factory Default Settings
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited
– see
Document Number: 001-56955 Rev. *N
PRTxRDM[1:0]
XRESMEN
DPS{1:0]
ECCEN
DIG_PHS_DLY[3:0]
Table
Register Address
“Nonvolatile Latches (NVL))”
5-2.
Field
0x00
0x01
0x02
0x03
Controls reset drive mode of the corresponding IO port.
See
are set to the same mode.
Controls whether pin P1[2] is used as a GPIO or as an
external reset. See
description.
Controls the usage of various P1 pins as a debug port.
See
page 59.
Controls whether ECC flash is used for ECC or for general
configuration and data storage. See
Memory”
Selects the digital clock phase delay.
XRESMEN
“Reset Configuration”
“Programming, Debug Interfaces, Resources”
PRT12RDM[1:0]
PRT3RDM[1:0]
7
on page 22.
on page
DIG_PHS_DLY[3:0]
“Pin Descriptions”
96.
6
Description
on page 40. All pins of the port
PRT2RDM[1:0]
PRT6RDM[1:0]
5
“Flash Program
on page 10, XRES
4
on
Table
ECCEN
PRT1RDM[1:0]
PRT5RDM[1:0]
3
00b (default) - high impedance analog
01b - high impedance digital
10b - resistive pull up
11b - resistive pull down
0 (default for 68-pin and 100-pin parts) - GPIO
1 (default for 48-pin parts) - external reset
00b - 5-wire JTAG
01b (default) - 4-wire JTAG
10b - SWD
11b - debug ports disabled
0 (default) - ECC disabled
1 - ECC enabled
See the TRM for details.
5-3:.
PSoC
2
DPS[1:0]
®
3: CY8C32 Family
Settings
1
PRT15RDM[1:0]
PRT0RDM[1:0]
PRT4RDM[1:0]
Data Sheet
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