AMIS30421C4211G ONSEMI [ON Semiconductor], AMIS30421C4211G Datasheet - Page 27

• Manufacturer Part Number: AMIS30421C4211G
• Description: Micro-Stepping Stepper Motor Bridge Controller
• Manufacturer: ONSEMI [ON Semiconductor]

‘0’. This simple mechanism protects against noise and
increases the consistency of the transmitted data. If a parity
check error occurs it is recommended to initiate an
additional READ command to obtain the status again.
successive READ commands as illustrated in Figure 28.
There is one exception. In case an error condition occurs the
WRITE Operation
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CSb goes from low to high. It is important that
the writing action to the Control Register is exactly 16 bits
long and that CSb goes high after these 16 bits. If more or
Examples of READ and WRITE Operations
WRITE operations are combined. In Figure 28 the Master
first reads the status from Register at Addr1 and at Addr2
READ command in order to verify the data correctly written
as illustrated in Figure 29. During reception of the READ
The CSb−pin is active low and may remain low between
If the Master wants to write data to a Control Register it
In the following examples successive READ and/or
After a WRITE operation the Master could initiate a
CLK
CLK
DO
DO
CS
CS
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DI
DI
Data from previous command or not valid after POR .
Data from previous command or not valid after POR .
Old Data or
Old Data or
Not Valid
Not Valid
Figure 27. Single WRITE Operation Where Data from the Master is Written in SPI Register
Figure 26. Single READ Operation Where Data from SPI Register is Read by the Master
0
1
Old Data or
Old Data or
Not Valid
Not Valid
Figure 28. 2 Successive READ Commands Followed by a WRITE Command
0
0
DO
CS
DI
Old Data or
Old Data or
Not Valid
Not Valid
0
0
Old Data or
Old Data or
Addr[4]
Addr[4]
Not Valid
Not Valid
Old Data or
from Addr1
Read Data
Not Valid
Old Data or
Old Data or
Addr[3]
Addr[3]
Not Valid
Not Valid
Old Data or
Old Data or
Data from previous command
or not valid after POR
Addr[2]
Addr[2]
Not Valid
Not Valid
Data from Addr1
Old Data or
Old Data or
Addr[1]
Addr[1]
from Addr2
Not Valid
Not Valid
Read Data
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Old Data or
Old Data or
Addr[0]
Addr[0]
Not Valid
Not Valid
27
Next command or dummy data
Command or
Old data from Addr
D[7] from
D[7] from
From Addr
Old Data
Dummy
root cause of the problem can be determined by reading out
the Status Registers. However, if the error occurs at the
moment CSb is low, one first needs to pull CSb high to
update the Status Registers properly. Only then the Status
Registers can be read out to determine the error. For this
reason it is also recommended to keep CSb high when the
SPI bus is idle.
less bits are transmitted the complete transfer packet is
ignored.
(e.g. Status Registers) will not affect the addressed register
and the device operation.
shifting out via DO the data stored in the last received
address. Because after a power−on−reset the initial address
is unknown the data shifted out via DO is not valid.
followed by writing a control byte in Control Register at
Addr3. Note that during the WRITE command the old data
of the pointed register is returned at the moment the new data
is shifted in.
command the old data is returned for a second time. Only
after receiving the READ command the new data is
transmitted. This rule also applies when the master device
Addr
Addr
Data from Addr2
A WRITE command executed for a read−only register
AMIS−30421 responds on every incoming byte by
Write Data
to Addr3
Command or
D[6 ] from
D[6 ] from
From Addr
Old Data
Dummy
Addr
Addr
New data is written into Register
with Addr3 at rising edge of CSb
Command or
D[5] from
D[5] from
From Addr
Old Data
Dummy
Addr
Addr
Command or
D[4 ] from
D[4 ] from
From Addr
Old Data
Dummy
Addr
Addr
from Addr3
New Data
Old Data
to Addr 3
Command or
D[3] from
D[3] from
From Addr
The new data is written into the corresponding
internal register at the rising edge of CS.
Old Data
Dummy
Addr
Addr
Command or
D[2 ] from
D[2 ] from
From Addr
Old Data
Dummy
Addr
Addr
Command or
D[1] from
D[1] from
From Addr
Old Data
Dummy
Addr
Addr
Command or
D[0 ] from
D[0 ] from
From Addr
Old Data
Dummy
Addr
Addr
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