AMIS30421C4211G ONSEMI [ON Semiconductor], AMIS30421C4211G Datasheet - Page 33

• Manufacturer Part Number: AMIS30421C4211G
• Description: Micro-Stepping Stepper Motor Bridge Controller
• Manufacturer: ONSEMI [ON Semiconductor]

Remark: Bit 5 of Control Register 2 should always be ‘0’ (zero)!
Status Register 0 (SR0)
the value of the register can change without the need of reading out the register. The register can be used to retrieve the
temperature range or to verify a watchdog event.
Notice that bit 7 is the parity bit (see READ operation p26).
Status Register 1 (SR1)
the bit will be set and can only be cleared by reading out this bit
the X−coil, or to report a charge pump failure.
Notice that bit 7 is the parity bit (see READ operation p26).
Table 16. CONTROL REGISTER 2 PARAMETERS
Table 17. STATUS REGISTER 0
Table 18. STATUS REGISTER 0 PARAMETERS
Table 19. STATUS REGISTER 1
Status Register 0 is located at address 0x04 and can only be read. Status Register 0 is a non−latched register meaning that
Status Register 1 is located at address 0x05 and can only be read. Status Register 1 is a latched register. If an error occurs
Address
Address
Parameter
0x05
1. In Sleep mode the register can be read out but will not be cleared!
SLA_OFFS
0x04
Parameter
TR[1:0]
WD
Access
Access
Reset
Data
Reset
Data
Value
Value
00
01
10
11
0
1
0
1
Watchdog event occurred
Bit 7
TSD = 0: 150°C to 170°C
PAR
Bit 7
PAR
R
0
R
0
No additional offset
No watchdog event
Additional offset of
TSD = 1: >170°C
−40°C to 15°C
73°C to 150°C
15°C to 72°C
Value
Value
0.6 V
OVCXPT
Bit 6
Bit 6
R
0
R
0
TR[1:0]
Status Register 0 (SR0)
Status Register 1 (SR1)
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OVCXPB
Bit 5
Bit 5
To enable an additional offset on the SLA−pin of 0.6V.
R
0
R
0
Motor driver thermal range.
Remark:
TR[1:0] = 11 and TSD = 0 => Thermal Warning
TR[1:0] = 11 and TSD = 1 => Thermal Shutdown
TSD is located in Status Register 2
If WDEN = 1 and watchdog not acknowledged before the
Watchdog Time−out (WDT[3:0]), WDb−pin will be pulled
low for 100ms to reset an external microcontroller and WD
bit will be set to ‘1’ to indicate this event. The external mi-
crocontroller can use this bit to verify a cold (WD = 0) or
warm boot (WD = 1).
33
1
. The register is used to report an overcurrent or open coil in
OVCXNT
Bit 4
Bit 4
WD
R
0
R
0
OVCXNB
Description
Description
Bit 3
Bit 3
R
0
R
0
−
CPFAIL
Bit 2
Bit 2
R
0
R
1
−
OPEN_X
Bit 1
Bit 1
R
0
R
0
−
p23
Bit 0
Bit 0
Info
Info
p20
p24
R
R
0
−
0
−