FIN24AC_07 FAIRCHILD [Fairchild Semiconductor], FIN24AC_07 Datasheet
FIN24AC_07
Related parts for FIN24AC_07
FIN24AC_07 Summary of contents
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FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Features ■ Low power for minimum impact on battery life – Multiple power-down modes – AC coupling with DC balance ■ 100nA in standby mode, 5mA typical operating conditions ■ Cable reduction: 25:4 or greater ■ ...
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Functional Block Diagram CKREF STROBE DP[21:22] DP[1:20] DP[23:24] CKP S1 S2 DIRI © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Word PLL 0 Boundary Generator I cksint Serializer Control Serializer oe Deserializer Deserializer cksint Control WORD CK Generator Control Logic ...
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Terminal Description Terminal Name I/O Type DP[1:20] I/O DP[21:22] I DP[23:24] O CKREF IN STROBE IN CKP OUT DSO+ / DSI– DIFF-I/O DSO– / DSI+ CKSI+, CKSI– DIFF-IN CKSO+, CKSO– DIFF-OUT DIRI IN DIRO OUT V ...
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Connection Diagrams DP[10] DP[11] DP[12] DP[13] DP[14] DP[15] DP[16] Figure 2. Terminal Assignments for MLP (Top View (Top View) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 ...
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Control Logic Circuitry The FIN24AC has the ability to be used as a 24-bit Seri- alizer or a 24-bit Deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 ...
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Serializer Operation Mode The serializer configurations are described in the following sections. The basic serialization circuitry works essentially the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the ...
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Serializer Operation Mode Serializer Operation: (Figure 6), DIRI = 1, No CKREF CKSI DP[1:24] WORD n-1 STROBE DSO CKS0 No Data Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) © 2005 ...
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Deserializer Operation Mode The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct ...
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Embedded Word Clock Operation The FIN24AC sends and receives serial data source synchronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has been ...
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From – Serializer From Control + To – Deserializer Figure 10. Bi-Directional Differential I/O Circuitry PLL Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL generates internal timing signals capa- ble of ...
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Application Mode Diagrams CKREF_M STROBE_M DP[1:12]_M Master Device Operating as a Serializer DIR = “1” “0” Figure 11. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 11 shows basic operation when a pair of SerDes ...
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Base Unit LCD Unit VSYNC/HSYNC Camera Unit GPIO Figure 13. Multiple Units, Unidirectional Signals in Each Direction Figure 13 shows a half-duplex connectivity diagram. This connectivity allows for two unidirectional data streams to be sent across a single pair of ...
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Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi- tion, ...
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DC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter LVCMOS I/O V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage OL ...
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Power Supply Currents Symbol Parameter V Serializer Static DDA I DDA1 Supply Current V Deserializer Static DDA I DDA2 Supply Current V Serializer Static Supply DDS I DDS1 Current V Deserializer Static Supply DDS I DDS2 Current V Power-Down Supply ...
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Symbol Parameter f Maximum Serial Data Rate MAX t DP Setup to STROBE STC ( Hold to STROBE HTC (n) f CKREF Frequency Relative to REF Strobe Frequency SERIALIZER AC ELECTRICAL CHARACTERISTICS t Transmitter Clock Input to TCCD ...
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Control Logic Timing Controls Symbol Parameter t , Propagation Delay PHL_DIR t DIRI-to-DIRO PLH_DIR Propagation Delay PLZ PHZ DIRI-to- Propagation Delay PZL PZH DIRI-to- Deserializer Disable Time: PLZ PHZ S0 or ...
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AC Loading and Waveforms Input Figure 14. Differential CTL Output DC Test Circuit DP[1:12] 666h CKREF CKS0- CKS0 Note: The “worst-case” test pattern produces a maximum toggling of ...
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AC Loading and Waveforms Setup Time t STC STROBE DP[1:12] Hold Time STROBE DP[1:12] Data Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1” Figure 19. Serial Setup and Hold Time Data Valid CKP Data DP[1:12] t ...
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AC Loading and Waveforms t S_DS CKSI- V DIFF=0 CKSI+ DSI DIFF=0 ID DSI- Figure 25. Differential Input Setup and Hold Times t TPPLD0 CKREF CKS0 Note: CKREF Signal can be stopped either HIGH or LOW. Figure ...
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Tape and Reel Specification Dimensions are in millimeters unless otherwise noted. BGA Embossed Tape Dimension ±0.1 ±0.1 ±0.05 Package 3.5 x 4.5 TBD TBD 1.55 Note: 10. ...
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Tape and Reel Specification Dimensions are in millimeters unless otherwise noted. MLP Embossed Tape Dimension ±0.1 ±0.1 ±0.05 Package 5.35 5.35 1. ...
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Physical Dimensions Dimensions are in millimeters unless otherwise noted. 2X 0.10 C TERMINAL A1 CORNER INDEX AREA (QA CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), ...
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Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (DATUM A) 24 www.fairchildsemi.com ...
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Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 25 www.fairchildsemi.com ...