74LCX240MSA_08 FAIRCHILD [Fairchild Semiconductor], 74LCX240MSA_08 Datasheet

74LCX240MSA_08

Manufacturer Part Number

74LCX240MSA_08

Description

Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Manufacturer

FAIRCHILD [Fairchild Semiconductor]

Datasheet

1.74LCX240MSA_08.pdf (12 pages)

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74LCX240 Rev. 1.6.0

74LCX240

Low Voltage Octal Buffer/Line Driver with 5V Tolerant

Inputs and Outputs

Features

Note:

1. To ensure the high-impedance state during power up

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

74LCX240WM

74LCX240SJ

74LCX240MSA

74LCX240MTC

5V tolerant inputs and outputs

2.3V–3.6V V

6.5ns t

Power-down high impedance inputs and outputs

Supports live insertion/withdrawal

±24mA output drive (V

Implements p roprietary noise/EMI reduction circuitry

Latch-up performance exceeds 500mA

ESD performance:

– Human body model

– Machine model

or down, OE should be tied to V

resistor: the minimum value or the resistor is

determined by the current-sourcing capability of the

driver.

Number

All packages are lead free per JEDEC: J-STD-020B standard.

Order

max. (V

specifications provided

Package

Number

MSA20

MTC20

200V

M20B

M20D

3.3V), 10µA I

2000V

3.0V)

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

(1)

through a pull-up

max.

General Description

The LCX240 is an inverting octal buffer and line driver

designed to be employed as a memory address driver,

clock driver and bus oriented transmitter or receiver. The

device is designed for low voltage (2.5V or 3.3V) V

applications with capability of interfacing to a 5V signal

environment.

The LCX240 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Package Description

January 2008

www.fairchildsemi.com

Related parts for 74LCX240MSA_08

74LCX240MSA_08 Summary of contents

Page 1

Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Features 5V tolerant inputs and outputs 2.3V–3.6V V specifications provided CC 6.5ns t max. (V 3.3V), 10µ Power-down high impedance inputs and outputs Supports live ...

Page 2

Connection Diagram Pin Description Pin Names Description 3-STATE Output Enable Inputs –I Inputs –O Outputs 0 7 ©1994 Fairchild Semiconductor Corporation 74LCX240 Rev. 1.6.0 Logic Diagram Truth Tables Inputs OE I ...

Page 3

Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure ...

Page 4

DC Electrical Characteristics Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I Power-Off Leakage Current OFF I ...

Page 5

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP V Quiet Output Dynamic Valley V OLV Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD ©1994 Fairchild Semiconductor Corporation 74LCX240 ...

Page 6

AC Loading and Waveforms Figure 1. AC Test Circuit (C Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t 3-STATE Output Low Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics 1MHz, t ...

Page 7

Page 8

Physical Dimensions 20 B 10.65 7.60 10.00 7.40 1 0.51 PIN ONE 0.35 INDICATOR 2.65 MAX 0.75 0.25 (R0.10) (R0.10) 8° 0° 1.27 0.40 SEATING PLANE (1.40) DETAIL A SCALE: 2:1 Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC ...

Page 9

Physical Dimensions (Continued) Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or ...

Page 10

Physical Dimensions (Continued) Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or ...

Page 11

Physical Dimensions (Continued) Figure 6. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision ...

Page 12

TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ ...

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