M28W320FSU STMICROELECTRONICS [STMicroelectronics], M28W320FSU Datasheet

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M28W320FSU

Manufacturer Part Number
M28W320FSU
Description
32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Uniform Block, Secure Flash Memories
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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FEATURES SUMMARY
May 2005
SUPPLY VOLTAGE
ACCESS TIME: 70ns
PROGRAMMING TIME:
COMMON FLASH INTERFACE
UNIFORM BLOCKS
64-KWord UNIFORM MEMORY BLOCKS
HARDWARE PROTECTION
SECURITY FEATURES
AUTOMATIC STAND-BY MODE
PROGRAM and ERASE SUSPEND
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
PACKAGE
V
V
V
10µs typical
Double Word Programming Option
Quadruple Word Programming Option
M28W320FSU: 32 Blocks
M28W640FSU: 64 Blocks
V
128 bit User-programmable OTP segment
64 bit Unique Device Identifier
KRYPTO Features:
Modify Protection,
Read Protection,
Device Authentication
Manufacturer Code: 20h
Device Codes:
M28W320FSU: 880Ch,
M28W640FSU: 8857h
Compliant with Lead-Free Soldering
Processes
Lead-Free Version
DD
DDQ
PP
PP
= 12V for fast Program (optional)
Pin for Write protect of All Blocks
= 2.7V to 3.6V Core Power Supply
= 2.7V to 3.6V for Input/Output
3V Supply, Uniform Block, Secure Flash Memories
32Mbit (2Mb x16) and 64Mbit (4Mb x16)
Figure 1. Package
TBGA64 (ZA)
M28W320FSU
M28W640FSU
10 x 13mm
BGA
1/49

Related parts for M28W320FSU

M28W320FSU Summary of contents

Page 1

... Double Word Programming Option – Quadruple Word Programming Option COMMON FLASH INTERFACE UNIFORM BLOCKS 64-KWord UNIFORM MEMORY BLOCKS – M28W320FSU: 32 Blocks – M28W640FSU: 64 Blocks HARDWARE PROTECTION – V Pin for Write protect of All Blocks PP SECURITY FEATURES – 128 bit User-programmable OTP segment – ...

Page 2

... Figure 1. Package SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. M28W320FSU Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. M28W640FSU Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. TBGA Connections (Top view through package Figure 5. M28W320FSU and M28W640FSU Block Addresses Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Inputs Data Input/Output (DQ0-DQ15 Chip Enable (E Output Enable (G) ...

Page 3

... Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16. Power-Up and Reset AC Characteristics PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 13.TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline . . . . . . . . 29 Table 17. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . . . 29 M28W320FSU, M28W640FSU 3/49 ...

Page 4

... M28W320FSU, M28W640FSU PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. Block Addresses, M28W320FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 21. Block Addresses, M28W640FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 APPENDIX B.COMMON FLASH INTERFACE (CFI Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. CFI Query Identification String Table 24. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 25 ...

Page 5

... SUMMARY DESCRIPTION The M28W320FSU and the M28W640FSU are 32 Mbit (2Mbit x 16) and 64 Mbit (4Mbit x 16) Secure Flash memories. The devices can be erased elec- trically at block level and programmed in-system on a Word-by-Word basis using a 2.7V to 3.6V V supply for the circuitry and a 2.7V to 3.6V ...

Page 6

... M28W320FSU, M28W640FSU Figure 2. M28W320FSU Logic Diagram DDQ A0-A20 W E M28W320FSU Table 1. Signal Names M28W320FSU A0-A20 DQ0-DQ15 DDQ 6/49 Figure 3. M28W640FSU Logic Diagram 16 A0-A21 DQ0-DQ15 AI10659 M28W640FSU A0-A21 Address Inputs Data Input/Output ...

Page 7

... DQ8 DQ1 F NC DQ0 Note: 1. The above figure gives the TBGA connections for M28W640FSU. On M28W320FSU, A21 is NC A12 A8 E A13 A6 A9 A11 A14 A4 A10 RP NC DQ9 DQ3 DQ4 ...

Page 8

... M28W320FSU, M28W640FSU Figure 5. M28W320FSU and M28W640FSU Block Addresses M28W320FSU Block Addresses 1FFFFFh 64 KWords 1F0000h 1EFFFFh 64 KWords 1E0000h 01FFFFh 64 KWords 010000h 00FFFFh 64 KWords 000000h Note: 1. Also see APPENDIX A., Tables Figure 6. Protection Register Memory Map 8Ch 85h 84h 81h 80h 8/49 3FFFFFh 3F0000h 3EFFFFh ...

Page 9

... Address Inputs. The Address Inputs select the cells in the memory array to access during Bus Read operations. Address Inputs range from A0 to A20 for the M28W320FSU. The M28W640FSU has an additional A21 address line. During Bus Write operations they control the commands sent to the Command Interface of the internal state ma- chine ...

Page 10

... M28W320FSU, M28W640FSU BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby, Automatic Standby and Re- set. See Table 2., Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations ...

Page 11

... All devices feature hardware protection. Refer to SIGNAL DESCRIPTIONS section for a detailed description of these signals. SECURITY FEATURES The M28W320FSU and M28W640FSU are equipped with KRYPTO Security features per- forming software protection. They allow any block to be protected from program/erase or read oper- ations: ...

Page 12

... M28W320FSU, M28W640FSU COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. The Pro- ...

Page 13

... Register should be cleared before attempting a new Program or Erase command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase M28W320FSU, M28W640FSU . As data integrity IL C., Figure 15., Double Word Pro- for the flow- is not set to V ...

Page 14

... M28W320FSU, M28W640FSU command and pause the Program/Erase control- ler. During Program/Erase Suspend the Command In- terface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electron- ic Signature and Read CFI Query commands. Ad- ditionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, or Protection Program commands will also be accepted ...

Page 15

... Device Manufacture Code M28W320FSU Device Code M28W640FSU Note Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU. Bus Write Operations 2nd Cycle 3rd Cycle Op. Add Data Op. Add Data Op. Add Data FFh RA RD Read ...

Page 16

... OTP OTP Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU. 16/49 (1) DQ0 80h Don't Care 0 81h Don't Care ID data 82h Don't Care ID data 83h Don't Care ID data ...

Page 17

... Double Word Program Quadruple Word Program Using Word Program command Using Double Word Block Program Program command Using Quadruple Word Program command Block Erase Program/Erase Cycles (per Block) Data Retention M28W320FSU, M28W640FSU M28W320FSU, M28W640FSU Test Conditions Min PPH ...

Page 18

... M28W320FSU, M28W640FSU STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, re- fer to Read Status Register Command section. To ...

Page 19

... Block Protection Status 0 Reserved Note: Logic level '1' is High, '0' is Low. M28W320FSU, M28W640FSU When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has been at- tempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register com- mand or a hardware reset ...

Page 20

... M28W320FSU, M28W640FSU MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 9 ...

Page 21

... Note: Sampled only, not 100% tested. M28W320FSU, M28W640FSU ment Conditions 10., Operating and AC Measurement Designers should check that the operating condi- tions in their circuit match the measurement condi- tions when relying on the quoted parameters. M28W320FSU, M28W640FSU Min 2.7 2.7 – Figure 8. AC Measurement Load Circuit V DDQ /2 ...

Page 22

... M28W320FSU, M28W640FSU Table 12. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Read) DD Supply Current (Stand- DD1 Automatic Stand-by) Supply Current I DD2 (Reset) I Supply Current (Program) DD3 I Supply Current (Erase) DD4 Supply Current I DD5 (Program/Erase Suspend) ...

Page 23

... Figure 9. Read AC Waveforms A0-A20/A21 ( DQ0-DQ15 ADDR. VALID CHIP ENABLE Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU. Table 13. Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid ...

Page 24

... M28W320FSU, M28W640FSU Figure 10. Write AC Waveforms, Write Enable Controlled Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU. 24/49 ...

Page 25

... Write Enable High to Write Enable Low WHWL WPH t t Write Enable Low to Write Enable High WLWH WP Note: 1. Sampled only, not 100% tested. 2. Applicable seen as a logic input (V PP Parameter Low PP < 3.6V). PP M28W320FSU, M28W640FSU M28W320FSU M28W640FSU 70 70 Min 70 70 Min 45 45 Min 45 45 Min 0 0 ...

Page 26

... M28W320FSU, M28W640FSU Figure 11. Write AC Waveforms, Chip Enable Controlled Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU. 26/49 ...

Page 27

... Note: 1. Sampled only, not 100% tested. 2. Applicable seen as a logic input (V PP Parameter Min Min Min Min Min Min Min Min Min Min Low Min PP Min Min < 3.6V). PP M28W320FSU, M28W640FSU M28W320FSU M28W640FSU ...

Page 28

... M28W320FSU, M28W640FSU Figure 12. Power-Up and Reset AC Waveforms tVDHPH VDD, VDDQ Table 16. Power-Up and Reset AC Characteristics Symbol Parameter t PHWL Reset High to Write Enable Low, Chip Enable Low, t PHEL Output Enable Low t PHGL (1,2) Reset Low to Reset High t PLPH (3) Supply Voltages High to Reset High ...

Page 29

... M28W320FSU, M28W640FSU ddd A2 BGA-Z23 inches Typ Min 0.0118 0.0079 0.0315 0.0138 0.3937 0.3898 0.2756 – 0.0394 – 0.5118 0.5079 0.2756 – ...

Page 30

... Mbit (4 Mb x16), Uniform Block, Secure, 0.13µm Speed 70 = 70ns Package ZA = TBGA64:10 x 13mm, 1mm pitch Temperature Range ° – °C Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing 30/49 M28W320FSU ...

Page 31

... F = Lead-Free and RoHS Package, Tape & Reel Packing Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. M28W320FSU, M28W640FSU M28W640FSU -ZA T ...

Page 32

... M28W320FSU, M28W640FSU APPENDIX A. BLOCK ADDRESS TABLES Table 20. Block Addresses, M28W320FSU Block Address Range Number 31 1F0000h-1FFFFFh 30 1E0000h-1EFFFFh 29 1D0000h-1DFFFFh 28 1C0000h-1CFFFFh 27 1B0000h-1BFFFFh 26 1A0000h-1AFFFFh 25 190000h-19FFFFh 24 180000h-18FFFFh 23 170000h-17FFFFh 22 160000h-16FFFFh 21 150000h-15FFFFh 20 140000h-14FFFFh 19 130000h-13FFFFh 18 120000h-12FFFFh 17 110000h-11FFFFh 16 100000h-10FFFFh 32/49 Block Address Range Number 15 0F0000h-0FFFFFh 14 0E0000h-0EFFFFh 13 0D0000h-0DFFFFh 12 0C0000h-0CFFFFh 11 0B0000h-0BFFFFh 10 0A0000h-0AFFFFh 9 090000h-09FFFFh ...

Page 33

... M28W320FSU, M28W640FSU Block Address Range Number 31 1F0000h-1FFFFFh 30 1E0000h-1EFFFFh 29 1D0000h-1DFFFFh 28 1C0000h-1CFFFFh 27 1B0000h-1BFFFFh 26 1A0000h-1AFFFFh 25 190000h-19FFFFh 24 180000h-18FFFFh 23 170000h-17FFFFh 22 160000h-16FFFFh 21 150000h-15FFFFh 20 140000h-14FFFFh 19 130000h-13FFFFh 18 120000h-12FFFFh 17 110000h-11FFFFh 16 100000h-10FFFFh 15 ...

Page 34

... Alternate Algorithm-specific Extended Query table Note: Query data are always presented on the lowest order data outputs. Table 23. CFI Query Identification String Offset Data 00h 0020h Manufacturer Code 880Ch M28W320FSU Device Code 01h 8857h M28W640FSU Device Code 02h-0Fh reserved Reserved 10h 0051h 11h 0052h Query Unique ASCII String " ...

Page 35

... Typical time-out for full chip erase = 2 23h 0005h Maximum time-out for Word program = 2 24h 0005h Maximum time-out for Double/Quadruple Word Program = 2 25h 0003h Maximum time-out per individual block erase = 2 26h 0000h Maximum time-out for chip erase = 2 M28W320FSU, M28W640FSU Description n µs n µ times typical n ...

Page 36

... M28W320FSU, M28W640FSU Table 25. Device Geometry Definition Offset Word Data Mode 0016h 27h Device Size = 2 0017h 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h Number of Erase Block Regions within the device. ...

Page 37

... Yes No) bit Reserved; undefined bits are ‘0’ Logic Supply Optimum Program/Erase voltage (highest performance) Supply Optimum Program/Erase voltage n = factory pre-programmed bytes n = user programmable bytes M28W320FSU, M28W640FSU Value "P" "R" "I" "1" "0" No ...

Page 38

... M28W320FSU, M28W640FSU Table 27. Security Code Area Offset Data 80h 00XX Protection Register Lock 81h XXXX 82h XXXX 64 bits: unique device number 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX 128 bits: User Programmable OTP 89h XXXX 8Ah ...

Page 39

... V PP Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ; Program if (status_register.b4==1) /*program error */ Error (1, 2) error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ Block Error (1, 2) error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PP M28W320FSU, M28W640FSU AI03538b 39/49 ...

Page 40

... M28W320FSU, M28W640FSU Figure 15. Double Word Program Flowchart and Pseudo Code Start Write 30h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Read Status Register YES YES YES NO Program to Protected Block Error (1, 2) YES End Note: 1. Status check of b1 (Protected Block sequence ...

Page 41

... Program error_handler ( ) ; Error ( (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PP M28W320FSU, M28W640FSU addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) /*see note (3) */ /*see note (3) */ /*see note (3) */ /*see note (3) */ AI06233 ...

Page 42

... M28W320FSU, M28W640FSU Figure 17. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another address Write D0h Program Continues 42/49 program_suspend_command ( ) { Program Complete if (status_register.b2==0) /*program completed */ ...

Page 43

... must be toggled*/ } while (status_register.b7 Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1) error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) Command /* command sequence error */ Sequence Error (1) error_handler ( ) ; if ( (status_register.b5== erase error */ Erase Error (1) error_handler ( ) ; Erase to Protected if (status_register.b1==1) /*program to protect block error */ Block Error (1) error_handler ( ) ; } M28W320FSU, M28W640FSU AI03541b 43/49 ...

Page 44

... M28W320FSU, M28W640FSU Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write D0h Erase Continues 44/49 erase_suspend_command ( ) { (status_register.b6==0) /*erase completed */ ...

Page 45

... V PP Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ; Program if (status_register.b4==1) /*program error */ Error (1, 2) error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ Block Error (1, 2) error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PP M28W320FSU, M28W640FSU AI04381 45/49 ...

Page 46

... M28W320FSU, M28W640FSU APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE Table 28. Write State Machine Current/Next, sheet Data Current SR Read When State bit 7 Array Read (FFh) Read Array “1” Array Read Array Prog.Setup Read “1” Status Read Array Status Read Electronic “ ...

Page 47

... Read CFI Query Erase Suspend Read CFI Query Erase Suspend Read CFI Query Erase Suspend Read CFI Query Read Elect.Sg. Read CFI Query M28W320FSU, M28W640FSU Prot. Prog. Setup (C0h) (98h) Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot ...

Page 48

... M28W320FSU, M28W640FSU REVISION HISTORY Table 30. Document Revision History Date Version 07-Dec-2004 0.1 07-Feb-2005 0.2 16-May-2005 1.0 48/49 Revision Details First Issue. Locations 31h to 34h set to reserved in Datasheet status updated to “Full Datasheet”. Table 25., Device Geometry Definition Table 25., Device Geometry Definition. updated. ...

Page 49

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