M28W320FSU STMICROELECTRONICS [STMicroelectronics], M28W320FSU Datasheet - Page 10

• Manufacturer Part Number: M28W320FSU
• Description: 32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Uniform Block, Secure Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M28W320FSU, M28W640FSU
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
able must be at V
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 9., Read AC
13., Read AC
the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at V
V
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
See
forms, and
Table 2. Bus Operations
Note: X = V
10/49
Bus Read
Bus Write
Output Disable
Standby
Reset
IH
. Commands, Input Data and Addresses are
Figure 10.
Operation
Table 2., Bus
IL
or V
Table 14.
IH
Characteristics, for details of when
, V
and
PPH
IL
in order to perform a read op-
= 12V ± 5%.
Figure
Operations, for a summary.
and
Waveforms, and
V
V
V
V
E
X
IH
IL
IL
IL
IL
with Output Enable at
11., Write AC Wave-
Table
15., Write AC
V
V
V
G
X
X
IH
IH
IL
Table
V
V
V
W
X
X
IH
IH
IL
Characteristics, for details of the timing require-
ments.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at V
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable is at V
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V
vice enters Standby mode when finished.
Automatic Standby. Automatic
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, V
current is reduced to I
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable
is Low, V
puts are high impedance. The memory is in Reset
mode when Reset is at V
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
able inputs. If Reset is pulled to V
gram or Erase, this operation is aborted and the
memory content is no longer valid.
IH
during a program or erase operation, the de-
V
V
V
V
RP
V
IH
IH
IH
IH
IL
IL
, the memory is deselected and the out-
V
Don't Care
Don't Care
Don't Care
Don't Care
DD
V
or V
PP
DD1
PPH
IL
IH
. The data Inputs/Out-
. The power consump-
and the device is in
IL
SS
, and the supply
Standby
Data Output
DQ0-DQ15
Data Input
during a Pro-
Hi-Z
Hi-Z
Hi-Z
IH
.
pro-