M28W320FSU STMICROELECTRONICS [STMicroelectronics], M28W320FSU Datasheet - Page 9

• Manufacturer Part Number: M28W320FSU
• Description: 32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Uniform Block, Secure Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SIGNAL DESCRIPTIONS
See Figures
1., Signal
nals connected to this device.
Address Inputs. The Address Inputs select the
cells in the memory array to access during Bus
Read operations. Address Inputs range from A0 to
A20 for the M28W320FSU. The M28W640FSU
has an additional A21 address line. During Bus
Write operations they control the commands sent
to the Command Interface of the internal state ma-
chine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V
mode. When Chip Enable is at V
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at V
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. After Reset all blocks are in the Locked
state. When Reset is at V
operation. Exiting reset mode the device enters
read array mode, but a negative transition of Chip
IL
and Reset is at V
Names, for a brief overview of the sig-
2
and 3, Logic Diagrams and
IH
IH
, the device is in normal
the device is in active
IH
the memory is
Table
IL
,
Enable or a change of the address is required to
ensure valid data outputs.
V
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
supply to the I/O pins and enables all Outputs to
be powered independently from V
tied to V
V
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage V
Program Supply Voltage V
any order.
If V
V
age lower than V
against program or erase, while V
ables these functions (see
teristics, for the relevant values). V
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase.
If V
In this condition V
gram/Erase algorithm is completed (see
and
mand will be ignored if V
a Double Word Program can be performed even if
V
V
measurements.
Note: Each device in a system should have
V
pacitor close to the pin. See
surement Load
should be sufficient to carry the required V
program and erase currents.
DD
DDQ
PP
PP
PP
SS
DD
PP
PP
, V
Table
Program Supply Voltage. V
is set to V
Ground. V
is seen as a control input. In this case a volt-
Supply Voltage. V
Supply Voltage. V
is set to V
is kept in a low voltage range (0V to 3.6V)
DDQ
DD
15.). A Quadruple Word Program com-
or can use a separate supply.
and V
DD.
M28W320FSU, M28W640FSU
PPH
PPLK
SS
Circuit. The PCB track widths
PP
PP
is the reference for all voltage
, it acts as a power supply pin.
decoupled with a 0.1µF ca-
must be stable until the Pro-
gives an absolute protection
PP
DD
DDQ
Table 12., DC Charac-
is not set to V
PP
provides the power
Figure 8., AC Mea-
provides the power
can be applied in
DD
PP
PP
. V
is both a
> V
DDQ
DD
PP
Table 14.
PPH
and the
PP1
is only
can be
while
9/49
en-
PP