M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet
M58WR032FB60ZB6
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M58WR032FB60ZB6 Summary of contents
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... Word typical for Fast Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options MEMORY BLOCKS – Multiple Bank Memory Array: 4 Mbit Banks – Parameter Blocks (Top or Bottom location) DUAL OPERATIONS – Program Erase in one Bank while Read in others – ...
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... FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. VFBGA Connections (Top view through package Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A20 Data Input/Output (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W Write Protect (WP) ...
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... Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Standard Commands Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Setup Phase ...
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M58WR032FT, M58WR032FB Data Output Configuration Bit (CR9 ...
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Figure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M58WR032FT, M58WR032FB Figure 28.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ...
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... Time-Programmable (OTP) by the user. The user programmable segment can be permanently pro- tected. Memory Map. The memory is offered in a VFBGA56, 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch package. In addition to the standard version, the package is also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive ...
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M58WR032FT, M58WR032FB Figure 2. Logic Diagram DDQ A0-A20 W E M58WR032FT G M58WR032FB SSQ 8/86 Table 1. Signal Names A0-A20 DQ0-DQ15 DQ0-DQ15 W RP ...
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Figure 3. VFBGA Connections (Top view through package A11 B A12 C A13 A10 D A15 A14 E V DDQ DQ15 DQ14 G DQ7 V SSQ Table 2. Bank Architecture Number Parameter Bank Bank 1 ...
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... M58WR032FT, M58WR032FB Figure 4. Memory Map M58WR032FT - Top Boot Block Address lines A20-A0 000000h 32 KWord 007FFFh Bank 7 038000h 32 KWord 03FFFFh 100000h 32 KWord 107FFFh Bank 3 138000h 32 KWord 13FFFFh 140000h 32 KWord 147FFFh Bank 2 178000h 32 KWord 17FFFFh 180000h 32 KWord 187FFFh Bank 1 1B8000h 32 KWord 1BFFFFh 1C0000h ...
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... Table 13., Lock Reset (RP). The Reset input provides a hard- ware reset of the memory. When Reset the memory is in reset mode: the outputs are high impedance and the current consumption is re- duced to the Reset Supply Current I Table 18., DC Characteristics - value of I After Reset all blocks are in the DD2 ...
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... Reset. During Reset mode the memory is dese- lected and the outputs are high impedance. The with IL memory is in Reset mode when Reset The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to ...
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... COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. The Pro- ...
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... See APPENDIX bles 30, 31, 32, 33, 34, 35, 36, 37, details on the information contained in the Com- mon Flash Interface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to ‘0’) error bits SR1, SR3, SR4 and SR5 in the Status Register. One bus write cycle is required to issue the Clear Status Register com- mand ...
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... Typical Program times are given in Table 14., Program/ Erase Times and Endurance Cycles. Programming aborts if Reset goes to V integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See APPENDIX C., Figure 22., Program Flow- chart and Pseudo Code, for the flowchart for using the Program command ...
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... Configuration Register content. The second cycle writes the Configuration Register data and the confirm command. Read operations output the memory array content after the Set Configuration Register command is issued. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc. ...
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The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 13. shows the Lock Status af- Table ...
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... Block Protection Locked and Locked-Down Unlocked and Locked-Down Reserved Configuration Register ST Factory Default Protection Register Lock OTP Area Permanently Locked Protection Register Note Configuration Register. Figure 5. Protection Register Memory Map 8Ch 85h 84h 81h 80h 18/86 Code PROTECTION REGISTER User Programmable OTP ...
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... Typical Program times are given in gram/Erase Times and Endurance Programming aborts if Reset goes to V integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See APPENDIX gram Flowchart and Pseudo chart for using the Double Word Program command ...
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... Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. The memory is now set to enter the Verify Phase. Verify Phase. The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data ...
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... Word of each Page as the order of the Words to be programmed is fixed. STATUS REG- The memory is now set to enter the Program and Verify Phase. Program and Verify Phase. In the Program and Verify Phase the four Words that were loaded in ...
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... A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and check that the memory is ready to accept the next data number of Words number of Pages to be programmed. 7. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent Words in each Page can be written to any address ...
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... Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to ‘1’), the ...
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... When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend com- mand has been issued and the memory is waiting for a Program/Erase Resume command. The Pro- gram Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive) ...
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Table 8. Status Register Bits Bit Name SR7 P/E.C. Status SR6 Erase Suspend Status SR5 Erase Status SR4 Program Status V Status SR3 PP SR2 Program Suspend Status Status SR1 Block Protection Status Bank Write Status SR0 Multiple Word Program ...
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... M58WR032FT, M58WR032FB CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. Refer to READ MODES on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1) ...
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The Wrap Burst bit is used to select be- tween wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not ...
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M58WR032FT, M58WR032FB Table 10. Burst Type Definition 4 Words Start Inter- Add Sequen-tial leaved 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 ... ...
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Words Start Inter- Add Sequen-tial Sequential leaved 0 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-4 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8- 2 2-3-4-5 3-4-5-6-7-8-9- 3 3-4-5-6 ... 7-8-9-10-11-12- 7 7-8-9-10 13-14 ... 12-13-14-15- 12 12-13-14-15 16-17-18-19 13-14-15- 13-14-15- 13 WAIT-16-17- WAIT-16 18-19-20 14-15- 14-15-WAIT- 14 WAIT- ...
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M58WR032FT, M58WR032FB Figure 6. X-Latency and Data Output Configuration Example 1st cycle A20-A0 VALID ADDRESS tDELAY tAVK_CPU DQ15-DQ0 Note. Settings shown: X-latency = 4, Data Output held for one clock cycle Figure 7. Wait Configuration Example E ...
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... It is pos- sible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read opera- tions, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchro- nous Read or Asynchronous Random Access CON- Read must be used ...
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... WAIT being gated by E remains active and will not revert to high-impedance when G goes high two or more devices are connected to the system’s READY signal, to prevent bus contention the WAIT signal of the Flash memory should not be di- rectly connected to the system’s READY signal. Syn- See Table 21 ...
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DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE The Multiple Bank Architecture M58WR032FT/B provides flexibility for software developers by allowing code and data to be split with 4Mbit granularity. The Dual Operations fea- ture simplifies the software management of the de- vice ...
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M58WR032FT, M58WR032FB BLOCK LOCKING The M58WR032FT/B features an instant, individu- al block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows ...
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Table 13. Lock Status Current (1) Protection Status (WP, DQ1, DQ0) Program/Erase Current State Allowed 1,0,0 yes (2) no 1,0,1 1,1,0 yes 1,1,1 no 0,0,0 yes (2) no 0,0,1 0,1,1 no Note: 1. The lock status is defined by the ...
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... Program/ Erase cycles per block are shown in ble 14. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block or bank are at ‘0’ (pre- programmed). The worst case is when all the bits in the block or bank are at ‘1’ (not prepro- Table 14 ...
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Parameter Parameter Block (4 KWord) Erase Main Block (32 KWord) Bank (4Mbit) Word/ Double Word/ Quadruple Word Parameter Block (4 KWord) (3) Program Main Block (32 KWord) Bank (4Mbit) Main Blocks Program/Erase Cycles (per Block) Parameter Blocks Note ...
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M58WR032FT, M58WR032FB MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...
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M58WR032FT, M58WR032FB Table 18. DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=54MHz) I DD1 Supply Current Synchronous Read (f=66MHz) I Supply Current ...
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Table 19. DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 Program Voltage Factory PPH ...
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M58WR032FT, M58WR032FB Figure 10. Asynchronous Random Access Read AC Waveforms 42/86 ...
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Figure 11. Asynchronous Page Read AC Waveforms M58WR032FT, M58WR032FB 43/86 ...
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M58WR032FT, M58WR032FB Table 20. Asynchronous Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid (Random) AVQV ACC t t Address Valid to Output Valid (Page) AVQV1 PAGE ...
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Figure 12. Synchronous Burst Read AC Waveforms M58WR032FT, M58WR032FB 45/86 ...
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M58WR032FT, M58WR032FB Figure 13. Single Synchronous Read AC Waveforms 46/86 ...
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Figure 14. Synchronous Burst Read Suspend AC Waveforms M58WR032FT, M58WR032FB 47/86 ...
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M58WR032FT, M58WR032FB Figure 15. Clock input AC Waveform tKHKL Table 21. Synchronous Read AC Characteristics Symbol Alt t t AVKH AVCLKH t t ELKH ELCLKH t ELTV t EHEL t EHTZ t t KHAX CLKHAX t KHQV t CLKHQV t ...
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Figure 16. Write AC Waveforms, Write Enable Controlled M58WR032FT, M58WR032FB 49/86 ...
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M58WR032FT, M58WR032FB Table 22. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH (3) Address Valid to Write Enable High t AVWH t ...
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Figure 17. Write AC Waveforms, Chip Enable Controlled M58WR032FT, M58WR032FB 51/86 ...
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M58WR032FT, M58WR032FB Table 23. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Chip Enable High AVEH t Address Valid to Latch Enable High AVLH t t ...
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Figure 18. Reset and Power-up AC Waveforms tVDHPH VDD, VDDQ Table 24. Reset and Power-up AC Characteristics Symbol Parameter Reset Low to t PLWL Write Enable Low, t PLEL Chip Enable Low, t PLGL Output ...
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M58WR032FT, M58WR032FB PACKAGE MECHANICAL Figure 19. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, ...
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Figure 20. VFBGA56 Daisy Chain - Package Connections (Top view through package M58WR032FT, M58WR032FB AI07731b 55/86 ...
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M58WR032FT, M58WR032FB Figure 21. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) 1 START POINT 56/ END POINT AI07755 ...
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... E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op- tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you ...
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M58WR032FT, M58WR032FB APPENDIX A. BLOCK ADDRESS TABLES Table 28. Top Boot Block Addresses, M58WR032FT Size Bank # Address Range (KWord 1FF000-1FFFFF 1 4 1FE000-1FEFFF 2 4 1FD000-1FDFFF 3 4 1FC000-1FCFFF 4 4 1FB000-1FBFFF 5 4 1FA000-1FAFFF 6 4 ...
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Table 29. Bottom Boot Block Addresses, M58WR032FB Size Bank # (KWord 1E8000-1EFFFF 1D8000-1DFFFF 65 32 1D0000-1D7FFF 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 1A8000-1AFFFF ...
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... Alternate Algorithm-specific Extended Query table 80h Security Code Area Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 31, 32, 33 and 34. Query data is always presented on the lowest order data outputs. ...
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Table 31. CFI Query Identification String Offset Sub-section Name 00h 0020h 8814h 01h 8815h 02h reserved 03h reserved 04h-0Fh reserved 10h 0051h 11h 0052h 12h 0059h 13h 0003h 14h 0000h 15h offset = P = 0039h 16h 0000h 17h 0000h ...
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M58WR032FT, M58WR032FB Table 32. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 1Bh 0017h bit BCD value in volts bit BCD value in 100 millivolts V ...
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Table 33. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0000h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h 2Ch ...
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M58WR032FT, M58WR032FB Table 34. Primary Algorithm-Specific Extended Query Table Offset Data (P)h = 39h 0050h 0052h Primary Algorithm extended Query table unique ASCII string “PRI” 0049h (P+3)h = 3Ch 0031h Major version number, ASCII (P+4)h = 3Dh 0033h Minor version ...
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Table 35. Protection Register Information Offset Data Number of protection register fields in JEDEC ID space. 0000h indicates that (P+E)h = 47h 0001h 256 fields are available. (P+F)h = 48h 0080h Protection Field 1: Protection Description Bits 0-7 Lower byte ...
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M58WR032FT, M58WR032FB Table 38. Bank and Erase Block Region 1 Information M58WR032FT (top) M58WR032FB(bottom) Offset Data Offset (P+1A)h = 53h 07h (P+1A)h = 53h (P+1B)h = 54h 00h (P+1B)h = 54h (P+1C)h = 55h 11h (P+1C)h = 55h (P+1D)h = ...
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M58WR032FT (top) M58WR032FB(bottom) Offset Data Offset (P+2E)h = 67h (P+2F)h = 68h Note: 1. The variable pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Table 39. Bank and ...
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M58WR032FT, M58WR032FB M58WR032FT (top) M58WR032FB (bottom) Offset Data Offset (P+35)h = 6Eh 03h (P+3D)h = 76h (P+36)h = 6Fh 07h (P+37)h = 70h 00h (P+38)h = 71h 20h (P+39)h = 72h 00h (P+3A)h = 73h 64h (P+3B)h = 74h 00h ...
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... Any address within the bank can equally be used. program_command (addressToProgram, dataToProgram) {: " writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ " writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 Invalid if (status_register.SR3==1) /*V PP invalid error */ Error (1, 2) error_handler ( ) ...
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... Any address within the bank can equally be used. 70/86 double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (addressToProgram1, 0x35); writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; /*Memory enters read status state after the Program command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 Invalid if (status_register.SR3==1) /*V PP invalid error */ Error (1, 2) error_handler ( ) ...
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... Any address within the bank can equally be used. quadruple_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (addressToProgram1, 0x56); writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; writeToFlash (addressToProgram3, dataToProgram3) ; writeToFlash (addressToProgram4, dataToProgram4) ; /*Memory enters read status state after the Program command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 Invalid if (status_register.SR3==1) /*V PP invalid error */ Error (1, 2) error_handler ( ) ...
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M58WR032FT, M58WR032FB Figure 25. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR2 = 1 YES Write FFh Read data from another address Write D0h (1) ...
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... Note error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can be used also. erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; writeToFlash (blockToErase, 0xD0 only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase must be toggled*/ } while (status_register.SR7 ...
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M58WR032FT, M58WR032FB Figure 27. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block or Program/Protection Register ...
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Figure 28. Locking Operations Flowchart and Pseudo Code Start Write 60h (1) Write 01h, D0h or 2Fh Write 90h (1) Read Block Lock States Locking change confirmed? YES Write FFh (1) End Note: 1. Any address within the bank can ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 76/86 protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 ...
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Figure 30. Enhanced Factory Program Flowchart SETUP PHASE NO Check SR4, SR3 and SR1 for program, V and Lock Errors PP Exit PROGRAM PHASE Address Block WA1 Note: 1. Address can remain Starting Address WA1 or be incremented. Start Write ...
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M58WR032FT, M58WR032FB Enhanced Factory Program Pseudo Code efp_command(addressFlow,dataFlow, the number of data to be programmed */ { /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ if (status_register.SR3==1) ...
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Figure 31. Quadruple Enhanced Factory Program Flowchart SETUP PHASE Start Write 75h Address WA1 FIRST LOAD PHASE Write PD1 Address WA1 Read Status Register NO SR7 = 0? YES Check SR4, SR3 and SR1 for program, PROGRAM AND V and ...
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M58WR032FT, M58WR032FB Quadruple Enhanced Factory Program Pseudo Code quad_efp_command(addressFlow,dataFlow, the number of pages to be programmed.*/ { /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data ...
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APPENDIX D. COMMAND INTERFACE STATE TABLES Table 40. Command Interface States - Modify Table, Next State WP Read Current CI State setup (2) Array (3,4) (FFh) (10/40h) Program Ready Ready Setup Lock/CR Setup Setup OTP Busy Setup Busy Program Suspend ...
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M58WR032FT, M58WR032FB Table 41. Command Interface States - Modify Table, Next Output WP Read Current CI State setup (2) Array (3,4) (FFh) (10/40h) Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad ...
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Table 42. Command Interface States - Lock Table, Next State Lock/CR Current CI State (4) Setup (60h) Lock/CR Ready Setup Lock/CR Setup Ready (Lock error) Setup OTP Busy Setup Program Busy Suspend Setup Busy Lock/CR Erase Setup in Suspend Erase ...
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M58WR032FT, M58WR032FB Table 43. Command Interface States - Lock Table, Next Output Lock/CR OTP Setup Current CI State (3) Setup (60h) Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup ...
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REVISION HISTORY Table 44. Document Revision History Date Version 21-Jan-2004 1.0 18-Nov-2004 2.0 Revision Details First Issue I values for Program/Erase in one Bank, Synchronous read in another Bank DD6 changed in Table 18., DC Characteristics - Figure 25., Program ...
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M58WR032FT, M58WR032FB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...