M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet - Page 20

• Manufacturer Part Number: M58WR032FB60ZB6
• Description: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58WR032FT, M58WR032FB
Read operations to the bank being programmed
output the Status Register content after the pro-
gramming has started.
Programming aborts if Reset goes to V
integrity cannot be guaranteed when the program
operation is aborted, the memory locations must
be reprogrammed.
During Quadruple Word Program operations the
bank being programmed will only accept the Read
Array, Read Status Register, Read Electronic Sig-
nature and Read CFI Query command, all other
commands will be ignored.
Dual operations are not supported during Quadru-
ple Word Program operations and the command
cannot be suspended. Typical Program times are
given in
durance
See
Program Flowchart and Pseudo
flowchart for using the Quadruple Word Program
command.
Enhanced Factory Program Command
The Enhanced Factory Program command can be
used to program large streams of data within any
one block. It greatly reduces the total program-
ming time when a large number of Words are writ-
ten to a block at any one time.
Dual operations are not supported during the En-
hanced Factory Program operation and the com-
mand cannot be suspended.
For optimum performance the Enhanced Factory
Program commands should be limited to a maxi-
mum of 10 program/erase cycles per block. If this
limit is exceeded the internal algorithm will contin-
ue to work properly but some degradation in per-
formance is possible. Typical Program times are
given in
The Enhanced Factory Program command has
four phases: the Setup Phase, the Program Phase
to program the data to the memory, the Verify
Phase to check that the data has been correctly
programmed and reprogram if necessary and the
Exit Phase. Refer to
Commands, and
Program
Setup Phase. The Enhanced Factory Program
command requires two Bus Write operations to ini-
tiate the command.
20/86
The fourth bus cycle latches the Address and
the Data of the third word to be written.
The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
The first bus cycle sets up the Enhanced
Factory Program command.
The second bus cycle confirms the command.
APPENDIX
Table 14., Program/Erase Times and En-
Table 14.
Cycles.
Flowchart.
C.,
Figure 30., Enhanced Factory
Figure 24., Quadruple Word
Table 7., Factory Program
Code, for the
IL
. As data
The Status Register P/E.C. Bit SR7 should be
read to check that the P/E.C. is ready. After the
confirm command is issued, read operations
output the Status Register data. The read Status
Register command must not be issued as it will be
interpreted as data to program.
Program Phase. The Program Phase requires
n+1 cycles, where n is the number of Words (refer
to
ure 30., Enhanced Factory Program
Three successive steps are required to issue and
execute the Program Phase of the command.
1. Use one Bus Write operation to latch the Start
2. Each subsequent Word to be programmed is
3. Finally, after all Words have been pro-
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data. The Program/Erase Controller
checks the stream of data with the data that was
programmed in the Program Phase and repro-
grams the memory location if necessary.
Three successive steps are required to execute
the Verify Phase of the command.
1. Use one Bus Write operation to latch the Start
2. Each subsequent Word to be verified is
Table 7., Factory Program
Address and the first Word to be programmed.
The Status Register Bank Write Status bit SR0
should be read to check that the P/E.C. is
ready for the next Word.
latched with a new Bus Write operation. The
address can either remain the Start Address,
in which case the P/E.C. increments the
address location or the address can be
incremented in which case the P/E.C. jumps to
the new address. If any address that is not in
the same block as the Start Address is given
with data FFFFh, the Program Phase
terminates and the Verify Phase begins. The
Status Register bit SR0 should be read
between each Bus Write cycle to check that
the P/E.C. is ready for the next Word.
grammed, write one Bus Write operation with
data FFFFh to any address outside the block
containing the Start Address, to terminate the
programming phase. If the data is not FFFFh,
the command is ignored.
Address and the first Word, to be verified. The
Status Register bit SR0 should be read to
check that the Program/Erase Controller is
ready for the next Word.
latched with a new Bus Write operation. The
Words must be written in the same order as in
the Program Phase. The address can remain
the Start Address or be incremented. If any
address that is not in the same block as the
Commands, and
Flowchart).
Fig-