M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet - Page 19

• Manufacturer Part Number: M58WR032FB60ZB6
• Description: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

COMMAND INTERFACE - FACTORY PROGRAM COMMANDS
The Factory Program commands are used to
speed up programming. They require V
V
also operates at V
tory Program
following text descriptions.
The use of Factory Program commands requires
certain operating conditions.
Bank Erase Command
The Bank Erase command can be used to erase a
bank. It sets all the bits within the selected bank to
’1’. All previous data in the bank is lost. The Bank
Erase command will ignore any protected blocks
within the bank. If all blocks in the bank are pro-
tected then the Bank Erase operation will abort
and the data in the bank will not be changed. The
Status Register will not output any error.
Bank Erase operations can be performed at both
V
Two Bus Write cycles are required to issue the
command.
If the second bus cycle is not Write Bank Erase
Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if
Reset turns to V
guaranteed when the Erase operation is aborted,
the bank must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode un-
til a Read Array, Read CFI Query or Read Elec-
tronic Signature command is issued.
During Bank Erase operations the bank being
erased will only accept the Read Array, Read Sta-
tus Register, Read Electronic Signature and Read
CFI Query command, all other commands will be
ignored.
For optimum performance, Bank Erase com-
mands should be limited to a maximum of 100 Pro-
gram/Erase cycles per Block. After 100 Program/
Erase cycles the internal algorithm will still operate
properly but some degradation in performance
may occur.
PPH
PP
V
Erase comand),
V
Ambient temperature, T
The targeted block must be unlocked.
The first bus cycle sets up the Bank Erase
command.
The second latches the bank address in the
internal state machine and starts the Program/
Erase Controller.
= V
PP
DD
except for the Bank Erase command which
PPH
must be set to V
must be within operating range,
and V
Commands, in conjunction with the
PP
IL
PP
. As data integrity cannot be
= V
= V
DD
DD
PPH
. Refer to
.
A
(except for Bank
must be 25°C ± 5°C,
Table 7., Fac-
PP
to be at
Dual Operations are not supported during Bank
Erase operations and the command cannot be
suspended.
Typical Erase times are given in
gram/Erase Times and Endurance
Double Word Program Command
The Double Word Program command improves
the programming throughput by writing a page of
two adjacent words in parallel. The two words
must differ only for the address A0.
Three bus write cycles are necessary to issue the
Double Word Program command.
Read operations in the bank being programmed
output the Status Register content after the pro-
gramming has started.
During Double Word Program operations the bank
being programmed will only accept the Read Ar-
ray, Read Status Register, Read Electronic Signa-
ture and Read CFI Query command, all other
commands will be ignored. Dual operations are
not supported during Double Word Program oper-
ations and the command cannot be suspended.
Typical Program times are given in
gram/Erase Times and Endurance
Programming aborts if Reset goes to V
integrity cannot be guaranteed when the program
operation is aborted, the memory locations must
be reprogrammed.
See
gram Flowchart and Pseudo
chart for using the Double Word Program
command.
Quadruple Word Program Command
The Quadruple Word Program command im-
proves the programming throughput by writing a
page of four adjacent words in parallel. The four
words must differ only for the addresses A0 and
A1.
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
The first bus cycle sets up the Double Word
Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
The first bus cycle sets up the Double Word
Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and
the Data of the second word to be written.
APPENDIX
M58WR032FT, M58WR032FB
C.,
Figure 23., Double Word Pro-
code, for the flow-
Table 14., Pro-
Table 14., Pro-
Cycles.
Cycles.
IL
. As data
19/86