X4325 INTERSIL [Intersil Corporation], X4325 Datasheet
X4325
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X4325 Summary of contents
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... CC Reset logic DESCRIPTION The X4323, X4325 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Volt- age Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time ...
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... SDA 6 8 SCL X4323, X4325 SCL SDA SCL SDA V SS RST/RST Device Select Input Device Select Input Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V falls below the minimum V ...
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... X4323 ZAM X4325S8IZ-4.5A (Note) (Note) 3 X4323, X4325 PART V RANGE V RANGE CC TRIP MARKING (V) (V) X4325 F 2.7 to 5.5 2.55 to 2.7 X4325 ZF X4325 G X4325 ZG 4325 F 4325 FZ 4325 G 4325 GZ X4325 AN 2.85 to 3.0 X4325 ZAN X4325 AP X4325 ZAP 4325 AN 4325 ANZ 4325 AP 4325 APZ X4325 4.5 to 5.5 4.25 to 4.5 X4325 Z X4325 I X4325 ZI 4325 ...
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... NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4 X4323, X4325 PART V RANGE ...
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... Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. V THRESHOLD RESET PROCEDURE CC CC The X4323, X4325 is shipped with a standard V threshold ( The TRIP over normal operating and storage conditions. How- ever, in applications where the standard V ...
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... A0h Figure 3. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 6 X4323, X4325 Resetting the higher or This procedure is used to set the V TRIP voltage level. For example, if the current V and the new V be reset. When V thing less than 1.7V. This procedure must be used to TRIP set the voltage to a lower value ...
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... DONE Error TRIP The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, and WD0. The X4323, X4325 will not acknowl- edge any data bytes written after the first byte is entered. New V Applied = ...
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... The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X4323, X4325 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation ...
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... Figure 5. Valid Data Changes on the SDA Bus SCL SDA 9 X4323, X4325 – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device con- sisting of [02H, 06H, 02H] will reset all of the nonvola- tile bits in the Control Register to 0 ...
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... Data Output from Receiver Start 10 X4323, X4325 Serial Stop Condition All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence ...
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... Signals from the Slave 11 X4323, X4325 eight bits of data. After receiving the 8-bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the inter- nal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master ...
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... ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 11. 12 X4323, X4325 Address Pointer Address Ends Here 60 Addr = 8 Figure 11 ...
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... Signals from the Slave 13 X4323, X4325 Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition ...
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... Figure 14. Sequential Read Sequence Signals from Slave the Master Address SDA Bus 1 Signals from the Slave X4323, X4325 Addressing LAVE DDRESS YTE Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: – ...
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... Figure 15. X4323, X4325 Addressing Device Identifier (X1) (X0 Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – The WEL bit is set to ‘0’. In this state it is not possi- ble to write to the device. ...
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... Device Select Bits in the Slave Address Byte. (3) V Min. and V Max. are for reference only and are not tested X4323, X4325 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. .... -1.0V to +7V This is a stress rating only; functional operation of the SS ...
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... Cb Capacitive load for each bus line Notes: (1) Typical values are for T = 25°C and total capacitance of one bus line in pF. 17 X4323, X4325 = 5V) CC Parameter A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels = 0 ...
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... the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 18 X4323, X4325 t t HIGH LOW ...
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... RESET (X4325) RESET Output Timing Symbol V Reset Trip Point Voltage, X4323-4.5A, X4325-4.5A TRIP Reset Trip Point Voltage, X4323, X4325 Reset Trip Point Voltage, X4323-2.7A, X4325-2.7A Reset Trip Point Voltage, X4323-2.7, X4325-2.7 t Power-up Reset Time OUT PURST ( Detect to Reset/Output RPD CC ...
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... Program Voltage repeatability (Successive program operations. Programmed at tr TRIP 25°C Program variation after programming (0-75°C). (Programmed at 25°C.) tv TRIP V programming parameters are periodically sampled and are not 100% tested. TRIP 20 X4323, X4325 Min. 100 450 1 100 V TRIP t TSU 00h 01h or 03h 00h ...
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... Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 21 X4323, X4325 D (N/2)+1 (N/2) H ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 X4323, X4325 M8.173 8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE M ...