X4325 INTERSIL [Intersil Corporation], X4325 Datasheet - Page 9

• Manufacturer Part Number: X4325
• Description: CPU Supervisor with 32k EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Writing to the Control Register
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:
– Write a 02H to the Control Register to set the Write
– Write a 06H to the Control Register to set both the
– Write a value to the Control Register that has all the
– A read operation occurring between any of the
Figure 5. Valid Data Changes on the SDA Bus
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
control bits set to the desired state. This can be rep-
resented as 0xys t01r in binary, where xy are the
WD bits, and rst are the BP bits. (Operation pre-
ceeded by a start and ended with a stop). Since this
is a nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(0xys t11r) then the RWEL bit is set, but the WD1,
WD0, BP2, BP1 and BP0 bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
previous operations will not interrupt the register
write operation.
SDA
SCL
9
Data Stable
X4323, X4325
Data Change
– The RWEL bit cannot be reset without writing to the
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
Data Stable
May 25, 2006
FN8122.1