X4325 INTERSIL [Intersil Corporation], X4325 Datasheet - Page 8

• Manufacturer Part Number: X4325
• Description: CPU Supervisor with 32k EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4323, X4325 resets itself after the first byte is
read. The master should supply a stop condition to be
consistent with the bus protocol, but a stop is not
required to end this operation.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to the following
segments of the array.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
Table 1. Write Protect Enable Bit and WP Pin Function
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
0
0
0
0
1
1
1
1
HIGH
HIGH
LOW
WP
7
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
Protected Addresses
WPEN
0000h - FFFh
000h - 07Fh
000h - 0FFh
000h - 1FFh
None (factory setting)
000h - 03Fh
X
0
1
5
(Size)
None
None
Memory Array not
Block Protected
4
(128 bytes)
(256 bytes)
(512 bytes)
(64 bytes)
(4K bytes)
8
Writes OK
Writes OK
Writes OK
3
2
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
First Page (P1)
Full Array (All)
Array Lock
None
None
None
Block Protected
1
Memory Array
Writes Blocked
Writes Blocked
Writes Blocked
X4323, X4325
0
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of five blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit.
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes to the
block protected sections in the memory array cannot be
written and the block protect bits cannot be changed.
Only the sections of the memory array that are not
block protected can be written. Note that since the
WPEN bit is write protected, it cannot be changed
back to a LOW state; so write protection is enabled as
long as the WP pin is held HIGH.
WD1
Block Protect
Writes Blocked
0
0
1
1
Writes OK
Writes OK
Bits
WD0
0
1
0
1
Writes Blocked
Watchdog Time Out Period
WPEN Bit
Writes OK
Writes OK
disabled (factory setting)
600 milliseconds
200 milliseconds
1.4 seconds
Protection
Hardware
Software
Software
May 25, 2006
FN8122.1