X5648 INTERSIL [Intersil Corporation], X5648 Datasheet - Page 2

• Manufacturer Part Number: X5648
• Description: CPU Supervisor with 64Kbit SPI EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

PIN CONFIGURATION
PIN DESCRIPTION
(PDIP)
Pin
1
2
5
6
3
4
8
7
V
CS
WP
SO
SS
1, 7, 8, 14
(SOIC)
12, 13
2, 3
Pin
10
11
4
9
5
6
1
2
3
4
8-Lead PDIP
X5648/49
2
RESET/
RESET
Name
SCK
V
V
WP
SO
NC
CS
SI
CC
SS
8
7
6
5
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
main active until V
SET/RESET goes active if the watchdog timer is enabled and CS remains either
HIGH or LOW longer than the selectable watchdog time out period. A falling
edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
RESET/RESET
SCK
SI
V
CC
X5648, X5649
CC
rises above the minimum V
CC
V
NC
WP
NC
CS
CS
SO
SS
falls below the minimum V
Function
1
2
3
4
5
6
7
14-Lead SOIC
X5648/49
14
13
12
11
10
9
8
CC
sense level for 200ms. RE-
CC
V
RESET/RESET
SCK
NC
V
SI
NC
CC
CC
sense level. It will re-
March 17, 2005
FN8136.0